Lines Matching +full:enable +full:- +full:ssc
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
45 MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
61 MVS_INT_MASK = 0x154, /* Central int enable */
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
77 MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
84 /* ports 1-3 follow after this */
87 /* ports 5-7 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
113 VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
193 * bit 0: G3 (6.0Gbps) with SSC
224 /* 64-bit buffer address */
226 /* 22-bit length */
234 MVS_SGPIO_CFG0_ENABLE = (1 << 0), /* enable pins */
320 return x ? __ffs64(x) : -1; in mv_ffc64()