| /openbmc/linux/include/linux/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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| /openbmc/linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
19 'struct clk'.
29 clk, useful across many platforms, as well as an
30 implementation of the clock API in include/linux/clk.h.
31 Architectures utilizing the common struct clk should select
43 source "drivers/clk/versatile/Kconfig"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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| /openbmc/u-boot/drivers/clk/ |
| H A D | Kconfig | 3 config CLK config
11 choose the source for each clock.
15 depends on CLK && SPL && SPL_DM
21 used as U-Boot proper.
25 depends on CLK && TPL_DM
31 used as U-Boot proper.
35 depends on CLK && ARCH_BMIPS
43 depends on CLK
51 depends on CLK && (STM32F7 || STM32F4)
59 depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
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| H A D | clk_stm32h7.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32h7-clks.h>
120 u32 cr; /* 0x00 Source Control Register */
121 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
130 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
144 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
145 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
146 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
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| H A D | clk_stm32f.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
16 #include <dt-bindings/mfd/stm32f7-rcc.h>
147 struct stm32_rcc_regs *regs = priv->base; in configure_clocks()
148 struct stm32_pwr_regs *pwr = priv->pwr_regs; in configure_clocks()
149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks()
152 setbits_le32(®s->cr, RCC_CR_HSION); in configure_clocks()
153 writel(0, ®s->cfgr); /* Reset CFGR */ in configure_clocks()
154 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON in configure_clocks()
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| /openbmc/u-boot/drivers/clk/at91/ |
| H A D | clk-plladiv.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
14 static int at91_plladiv_clk_enable(struct clk *clk) in at91_plladiv_clk_enable() argument
19 static ulong at91_plladiv_clk_get_rate(struct clk *clk) in at91_plladiv_clk_get_rate() argument
21 struct pmc_platdata *plat = dev_get_platdata(clk->dev); in at91_plladiv_clk_get_rate()
22 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate()
23 struct clk source; in at91_plladiv_clk_get_rate() local
27 ret = clk_get_by_index(clk->dev, 0, &source); in at91_plladiv_clk_get_rate()
29 return -EINVAL; in at91_plladiv_clk_get_rate()
31 clk_rate = clk_get_rate(&source); in at91_plladiv_clk_get_rate()
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| H A D | clk-usb.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
23 static ulong at91_usb_clk_get_rate(struct clk *clk) in at91_usb_clk_get_rate() argument
25 struct pmc_platdata *plat = dev_get_platdata(clk->dev); in at91_usb_clk_get_rate()
26 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_get_rate()
27 struct clk source; in at91_usb_clk_get_rate() local
32 tmp = readl(&pmc->pcr); in at91_usb_clk_get_rate()
37 ret = clk_get_by_index(clk->dev, source_index, &source); in at91_usb_clk_get_rate()
41 return clk_get_rate(&source) / (usbdiv + 1); in at91_usb_clk_get_rate()
44 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate) in at91_usb_clk_set_rate() argument
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| /openbmc/qemu/hw/core/ |
| H A D | clock.c | 4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
21 #define CLOCK_PATH(_clk) (_clk->canonical_path)
23 void clock_setup_canonical_path(Clock *clk) in clock_setup_canonical_path() argument
25 g_free(clk->canonical_path); in clock_setup_canonical_path()
26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
39 clock_setup_canonical_path(clk); in clock_new()
41 return clk; in clock_new()
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| /openbmc/linux/drivers/clk/ux500/ |
| H A D | clk-prcmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
28 u8 source; member
36 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_prepare() local
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
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| H A D | u8500_of_clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
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| /openbmc/qemu/include/hw/ |
| H A D | clock.h | 4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
39 * clock store a value representing the clock's period in 2^-32ns unit.
41 * + periods from 2^-32ns up to 4seconds
65 * @source: source (or parent in clock tree) of the clock
66 * @children: list of clocks connected to this one (it is their source)
89 Clock *source; member
110 * @clk: clock
114 void clock_setup_canonical_path(Clock *clk);
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra114 has muxes for the
22 * source. This gives us a clock 'type' and exploits what commonality exists
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 * Clock source mux for each clock type. This just converts our enum into
59 * The extra column in each clock source array is used to store the mask
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra30 has muxes for the
22 * source. This gives us a clock 'type' and exploits what commonality exists
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 * Clock source mux for each clock type. This just converts our enum into
59 * The extra column in each clock source array is used to store the mask
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | spear-cpufreq.c | 2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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| /openbmc/linux/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp-zc1751-xm019-dc5.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra124 has muxes for the
22 * source. This gives us a clock 'type' and exploits what commonality exists
49 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
57 CLOCK_TYPE_NONE = -1, /* invalid clock type */
61 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
65 * Clock source mux for each clock type. This just converts our enum into
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2010-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra20 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
40 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
45 CLOCK_TYPE_NONE = -1, /* invalid clock type */
49 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
53 * Clock source mux for each clock type. This just converts our enum into
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra210 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
59 CLOCK_TYPE_NONE = -1, /* invalid clock type */
63 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
67 * Clock source mux for each clock type. This just converts our enum into
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| /openbmc/u-boot/drivers/clk/owl/ |
| H A D | clk_s900.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch-owl/clk_s900.h>
12 #include <asm/arch-owl/regs_s900.h>
15 #include <dt-bindings/clock/s900_cmu.h>
22 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0)); in owl_clk_init()
26 /* Source HOSC to DEV_CLK */ in owl_clk_init()
27 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); in owl_clk_init()
33 writel(bus_clk, priv->base + CMU_BUSCLK); in owl_clk_init()
38 core_pll = readl(priv->base + CMU_COREPLL); in owl_clk_init()
40 writel(core_pll, priv->base + CMU_COREPLL); in owl_clk_init()
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| /openbmc/linux/drivers/net/can/mscan/ |
| H A D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
21 #include <linux/clk.h>
38 { .compatible = "fsl,mpc5200-cdm", },
55 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
66 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
76 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
82 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
86 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8qm-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is disabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
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| /openbmc/u-boot/arch/arm/mach-stm32/ |
| H A D | Kconfig | 5 select CLK
21 select CLK
59 select CLK
75 source "arch/arm/mach-stm32/stm32f4/Kconfig"
76 source "arch/arm/mach-stm32/stm32f7/Kconfig"
77 source "arch/arm/mach-stm32/stm32h7/Kconfig"
|