1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20d1bb41aSBen Dooks /* linux/drivers/mmc/host/sdhci-s3c.c
30d1bb41aSBen Dooks *
40d1bb41aSBen Dooks * Copyright 2008 Openmoko Inc.
50d1bb41aSBen Dooks * Copyright 2008 Simtec Electronics
60d1bb41aSBen Dooks * Ben Dooks <ben@simtec.co.uk>
70d1bb41aSBen Dooks * http://armlinux.simtec.co.uk/
80d1bb41aSBen Dooks *
90d1bb41aSBen Dooks * SDHCI (HSMMC) support for Samsung SoC
100d1bb41aSBen Dooks */
110d1bb41aSBen Dooks
12017210d1SPaul Osmialowski #include <linux/spinlock.h>
130d1bb41aSBen Dooks #include <linux/delay.h>
140d1bb41aSBen Dooks #include <linux/dma-mapping.h>
150d1bb41aSBen Dooks #include <linux/platform_device.h>
16cc014f3eSArnd Bergmann #include <linux/platform_data/mmc-sdhci-s3c.h>
175a0e3ad6STejun Heo #include <linux/slab.h>
180d1bb41aSBen Dooks #include <linux/clk.h>
190d1bb41aSBen Dooks #include <linux/io.h>
2017866e14SMarek Szyprowski #include <linux/gpio.h>
2155156d24SMark Brown #include <linux/module.h>
22d5e9c02cSMark Brown #include <linux/of.h>
23d5e9c02cSMark Brown #include <linux/of_gpio.h>
24d5e9c02cSMark Brown #include <linux/pm.h>
259f4e8151SMark Brown #include <linux/pm_runtime.h>
260d1bb41aSBen Dooks
270d1bb41aSBen Dooks #include <linux/mmc/host.h>
280d1bb41aSBen Dooks
290d1bb41aSBen Dooks #include "sdhci.h"
300d1bb41aSBen Dooks
310d1bb41aSBen Dooks #define MAX_BUS_CLK (4)
320d1bb41aSBen Dooks
3357f83245SJaehoon Chung #define S3C_SDHCI_CONTROL2 (0x80)
3457f83245SJaehoon Chung #define S3C_SDHCI_CONTROL3 (0x84)
3557f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4 (0x8C)
3657f83245SJaehoon Chung
37e64aae82SJaehoon Chung #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
38e64aae82SJaehoon Chung #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
39e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
40e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
4157f83245SJaehoon Chung
4257f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
4357f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
4457f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
4557f83245SJaehoon Chung
4657f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
4757f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
4857f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
4957f83245SJaehoon Chung
50e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
51e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
52e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
53e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
54e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
5557f83245SJaehoon Chung
5657f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
5757f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
5857f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
5957f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
6057f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
6157f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
6257f83245SJaehoon Chung
63e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
64e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
65e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
66e64aae82SJaehoon Chung
6757f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
6857f83245SJaehoon Chung #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
69e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
70e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
71e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
7257f83245SJaehoon Chung
73e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
74e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
75e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
76e64aae82SJaehoon Chung #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
7757f83245SJaehoon Chung
7857f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
7957f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
8057f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
8157f83245SJaehoon Chung
8257f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
8357f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
8457f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
8557f83245SJaehoon Chung
8657f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
8757f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
8857f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
8957f83245SJaehoon Chung
9057f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
9157f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
9257f83245SJaehoon Chung #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
9357f83245SJaehoon Chung
9457f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
9557f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
9657f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
9757f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
9857f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
9957f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
10057f83245SJaehoon Chung
10157f83245SJaehoon Chung #define S3C64XX_SDHCI_CONTROL4_BUSY (1)
10257f83245SJaehoon Chung
1030d1bb41aSBen Dooks /**
1040d1bb41aSBen Dooks * struct sdhci_s3c - S3C SDHCI instance
1050d1bb41aSBen Dooks * @host: The SDHCI host created
1060d1bb41aSBen Dooks * @pdev: The platform device we where created from.
1070d1bb41aSBen Dooks * @ioarea: The resource created when we claimed the IO area.
1080d1bb41aSBen Dooks * @pdata: The platform data for this controller.
1090d1bb41aSBen Dooks * @cur_clk: The index of the current bus clock.
11046525bccSLee Jones * @ext_cd_irq: External card detect interrupt.
1110d1bb41aSBen Dooks * @clk_io: The clock for the internal bus interface.
11246525bccSLee Jones * @clk_rates: Clock frequencies.
1130d1bb41aSBen Dooks * @clk_bus: The clocks that are available for the SD/MMC bus clock.
11446525bccSLee Jones * @no_divider: No or non-standard internal clock divider.
1150d1bb41aSBen Dooks */
1160d1bb41aSBen Dooks struct sdhci_s3c {
1170d1bb41aSBen Dooks struct sdhci_host *host;
1180d1bb41aSBen Dooks struct platform_device *pdev;
1190d1bb41aSBen Dooks struct resource *ioarea;
1200d1bb41aSBen Dooks struct s3c_sdhci_platdata *pdata;
1213ac147faSTomasz Figa int cur_clk;
12217866e14SMarek Szyprowski int ext_cd_irq;
1230d1bb41aSBen Dooks
1240d1bb41aSBen Dooks struct clk *clk_io;
1250d1bb41aSBen Dooks struct clk *clk_bus[MAX_BUS_CLK];
1266eb28bdcSTomasz Figa unsigned long clk_rates[MAX_BUS_CLK];
1271771059cSRussell King
1281771059cSRussell King bool no_divider;
1290d1bb41aSBen Dooks };
1300d1bb41aSBen Dooks
1313119936aSThomas Abraham /**
13290cdaa84SKrzysztof Kozlowski * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
1333119936aSThomas Abraham * @sdhci_quirks: sdhci host specific quirks.
13446525bccSLee Jones * @no_divider: no or non-standard internal clock divider.
1353119936aSThomas Abraham *
1363119936aSThomas Abraham * Specifies platform specific configuration of sdhci controller.
1373119936aSThomas Abraham * Note: A structure for driver specific platform data is used for future
1383119936aSThomas Abraham * expansion of its usage.
1393119936aSThomas Abraham */
1403119936aSThomas Abraham struct sdhci_s3c_drv_data {
1413119936aSThomas Abraham unsigned int sdhci_quirks;
1421771059cSRussell King bool no_divider;
1433119936aSThomas Abraham };
1443119936aSThomas Abraham
to_s3c(struct sdhci_host * host)1450d1bb41aSBen Dooks static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
1460d1bb41aSBen Dooks {
1470d1bb41aSBen Dooks return sdhci_priv(host);
1480d1bb41aSBen Dooks }
1490d1bb41aSBen Dooks
1500d1bb41aSBen Dooks /**
1510d1bb41aSBen Dooks * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
1520d1bb41aSBen Dooks * @host: The SDHCI host instance.
1530d1bb41aSBen Dooks *
1540d1bb41aSBen Dooks * Callback to return the maximum clock rate acheivable by the controller.
1550d1bb41aSBen Dooks */
sdhci_s3c_get_max_clk(struct sdhci_host * host)1560d1bb41aSBen Dooks static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
1570d1bb41aSBen Dooks {
1580d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host);
159222a13c5STomasz Figa unsigned long rate, max = 0;
160222a13c5STomasz Figa int src;
1610d1bb41aSBen Dooks
162222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) {
163222a13c5STomasz Figa rate = ourhost->clk_rates[src];
1640d1bb41aSBen Dooks if (rate > max)
1650d1bb41aSBen Dooks max = rate;
1660d1bb41aSBen Dooks }
1670d1bb41aSBen Dooks
1680d1bb41aSBen Dooks return max;
1690d1bb41aSBen Dooks }
1700d1bb41aSBen Dooks
1710d1bb41aSBen Dooks /**
1720d1bb41aSBen Dooks * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
1730d1bb41aSBen Dooks * @ourhost: Our SDHCI instance.
1740d1bb41aSBen Dooks * @src: The source clock index.
1750d1bb41aSBen Dooks * @wanted: The clock frequency wanted.
1760d1bb41aSBen Dooks */
sdhci_s3c_consider_clock(struct sdhci_s3c * ourhost,unsigned int src,unsigned int wanted)1770d1bb41aSBen Dooks static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
1780d1bb41aSBen Dooks unsigned int src,
1790d1bb41aSBen Dooks unsigned int wanted)
1800d1bb41aSBen Dooks {
1810d1bb41aSBen Dooks unsigned long rate;
1820d1bb41aSBen Dooks struct clk *clksrc = ourhost->clk_bus[src];
1838880a4a5STomasz Figa int shift;
1840d1bb41aSBen Dooks
1858f4b78d9STomasz Figa if (IS_ERR(clksrc))
1860d1bb41aSBen Dooks return UINT_MAX;
1870d1bb41aSBen Dooks
188253e0a7cSJeongbae Seo /*
1893119936aSThomas Abraham * If controller uses a non-standard clock division, find the best clock
1903119936aSThomas Abraham * speed possible with selected clock source and skip the division.
191253e0a7cSJeongbae Seo */
1921771059cSRussell King if (ourhost->no_divider) {
193253e0a7cSJeongbae Seo rate = clk_round_rate(clksrc, wanted);
194253e0a7cSJeongbae Seo return wanted - rate;
195253e0a7cSJeongbae Seo }
196253e0a7cSJeongbae Seo
1976eb28bdcSTomasz Figa rate = ourhost->clk_rates[src];
1980d1bb41aSBen Dooks
19922003000STomasz Figa for (shift = 0; shift <= 8; ++shift) {
2008880a4a5STomasz Figa if ((rate >> shift) <= wanted)
2010d1bb41aSBen Dooks break;
2020d1bb41aSBen Dooks }
2030d1bb41aSBen Dooks
20422003000STomasz Figa if (shift > 8) {
20522003000STomasz Figa dev_dbg(&ourhost->pdev->dev,
20622003000STomasz Figa "clk %d: rate %ld, min rate %lu > wanted %u\n",
20722003000STomasz Figa src, rate, rate / 256, wanted);
20822003000STomasz Figa return UINT_MAX;
20922003000STomasz Figa }
21022003000STomasz Figa
2110d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
2128880a4a5STomasz Figa src, rate, wanted, rate >> shift);
2130d1bb41aSBen Dooks
2148880a4a5STomasz Figa return wanted - (rate >> shift);
2150d1bb41aSBen Dooks }
2160d1bb41aSBen Dooks
2170d1bb41aSBen Dooks /**
2180d1bb41aSBen Dooks * sdhci_s3c_set_clock - callback on clock change
2190d1bb41aSBen Dooks * @host: The SDHCI host being changed
2200d1bb41aSBen Dooks * @clock: The clock rate being requested.
2210d1bb41aSBen Dooks *
2220d1bb41aSBen Dooks * When the card's clock is going to be changed, look at the new frequency
2230d1bb41aSBen Dooks * and find the best clock source to go with it.
2240d1bb41aSBen Dooks */
sdhci_s3c_set_clock(struct sdhci_host * host,unsigned int clock)2250d1bb41aSBen Dooks static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
2260d1bb41aSBen Dooks {
2270d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host);
2280d1bb41aSBen Dooks unsigned int best = UINT_MAX;
2290d1bb41aSBen Dooks unsigned int delta;
2300d1bb41aSBen Dooks int best_src = 0;
2310d1bb41aSBen Dooks int src;
2320d1bb41aSBen Dooks u32 ctrl;
2330d1bb41aSBen Dooks
2341650d0c7SRussell King host->mmc->actual_clock = 0;
2351650d0c7SRussell King
2360d1bb41aSBen Dooks /* don't bother if the clock is going off. */
2371771059cSRussell King if (clock == 0) {
2381771059cSRussell King sdhci_set_clock(host, clock);
2390d1bb41aSBen Dooks return;
2401771059cSRussell King }
2410d1bb41aSBen Dooks
2420d1bb41aSBen Dooks for (src = 0; src < MAX_BUS_CLK; src++) {
2430d1bb41aSBen Dooks delta = sdhci_s3c_consider_clock(ourhost, src, clock);
2440d1bb41aSBen Dooks if (delta < best) {
2450d1bb41aSBen Dooks best = delta;
2460d1bb41aSBen Dooks best_src = src;
2470d1bb41aSBen Dooks }
2480d1bb41aSBen Dooks }
2490d1bb41aSBen Dooks
2500d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev,
2510d1bb41aSBen Dooks "selected source %d, clock %d, delta %d\n",
2520d1bb41aSBen Dooks best_src, clock, best);
2530d1bb41aSBen Dooks
2540d1bb41aSBen Dooks /* select the new clock source */
2550d1bb41aSBen Dooks if (ourhost->cur_clk != best_src) {
2560d1bb41aSBen Dooks struct clk *clk = ourhost->clk_bus[best_src];
2570d1bb41aSBen Dooks
2580f310a05SThomas Abraham clk_prepare_enable(clk);
2593ac147faSTomasz Figa if (ourhost->cur_clk >= 0)
2603ac147faSTomasz Figa clk_disable_unprepare(
2613ac147faSTomasz Figa ourhost->clk_bus[ourhost->cur_clk]);
2620d1bb41aSBen Dooks
2630d1bb41aSBen Dooks ourhost->cur_clk = best_src;
2646eb28bdcSTomasz Figa host->max_clk = ourhost->clk_rates[best_src];
2653ac147faSTomasz Figa }
2663ac147faSTomasz Figa
2673ac147faSTomasz Figa /* turn clock off to card before changing clock source */
2683ac147faSTomasz Figa writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
2690d1bb41aSBen Dooks
2700d1bb41aSBen Dooks ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
2710d1bb41aSBen Dooks ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
2720d1bb41aSBen Dooks ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
2730d1bb41aSBen Dooks writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
2740d1bb41aSBen Dooks
2756fe47179SThomas Abraham /* reprogram default hardware configuration */
2766fe47179SThomas Abraham writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
2776fe47179SThomas Abraham host->ioaddr + S3C64XX_SDHCI_CONTROL4);
2780d1bb41aSBen Dooks
2796fe47179SThomas Abraham ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
2806fe47179SThomas Abraham ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
2816fe47179SThomas Abraham S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
2826fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENFBCLKRX |
2836fe47179SThomas Abraham S3C_SDHCI_CTRL2_DFCNT_NONE |
2846fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
2856fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
2860d1bb41aSBen Dooks
2876fe47179SThomas Abraham /* reconfigure the controller for new clock rate */
2886fe47179SThomas Abraham ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
2896fe47179SThomas Abraham if (clock < 25 * 1000000)
2906fe47179SThomas Abraham ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
2916fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
2921771059cSRussell King
2931771059cSRussell King sdhci_set_clock(host, clock);
2940d1bb41aSBen Dooks }
2950d1bb41aSBen Dooks
296ce5f036bSMarek Szyprowski /**
297ce5f036bSMarek Szyprowski * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
298ce5f036bSMarek Szyprowski * @host: The SDHCI host being queried
299ce5f036bSMarek Szyprowski *
300ce5f036bSMarek Szyprowski * To init mmc host properly a minimal clock value is needed. For high system
301ce5f036bSMarek Szyprowski * bus clock's values the standard formula gives values out of allowed range.
302ce5f036bSMarek Szyprowski * The clock still can be set to lower values, if clock source other then
303ce5f036bSMarek Szyprowski * system bus is selected.
304ce5f036bSMarek Szyprowski */
sdhci_s3c_get_min_clock(struct sdhci_host * host)305ce5f036bSMarek Szyprowski static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306ce5f036bSMarek Szyprowski {
307ce5f036bSMarek Szyprowski struct sdhci_s3c *ourhost = to_s3c(host);
308222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX;
309ce5f036bSMarek Szyprowski int src;
310ce5f036bSMarek Szyprowski
311ce5f036bSMarek Szyprowski for (src = 0; src < MAX_BUS_CLK; src++) {
312222a13c5STomasz Figa rate = ourhost->clk_rates[src] / 256;
313222a13c5STomasz Figa if (!rate)
314ce5f036bSMarek Szyprowski continue;
315222a13c5STomasz Figa if (rate < min)
316222a13c5STomasz Figa min = rate;
317ce5f036bSMarek Szyprowski }
318222a13c5STomasz Figa
319ce5f036bSMarek Szyprowski return min;
320ce5f036bSMarek Szyprowski }
321ce5f036bSMarek Szyprowski
322253e0a7cSJeongbae Seo /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
sdhci_cmu_get_max_clock(struct sdhci_host * host)323253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324253e0a7cSJeongbae Seo {
325253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host);
326222a13c5STomasz Figa unsigned long rate, max = 0;
327222a13c5STomasz Figa int src;
328253e0a7cSJeongbae Seo
329222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) {
330222a13c5STomasz Figa struct clk *clk;
331222a13c5STomasz Figa
332222a13c5STomasz Figa clk = ourhost->clk_bus[src];
333222a13c5STomasz Figa if (IS_ERR(clk))
334222a13c5STomasz Figa continue;
335222a13c5STomasz Figa
336222a13c5STomasz Figa rate = clk_round_rate(clk, ULONG_MAX);
337222a13c5STomasz Figa if (rate > max)
338222a13c5STomasz Figa max = rate;
339222a13c5STomasz Figa }
340222a13c5STomasz Figa
341222a13c5STomasz Figa return max;
342253e0a7cSJeongbae Seo }
343253e0a7cSJeongbae Seo
344253e0a7cSJeongbae Seo /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
sdhci_cmu_get_min_clock(struct sdhci_host * host)345253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346253e0a7cSJeongbae Seo {
347253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host);
348222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX;
349222a13c5STomasz Figa int src;
350253e0a7cSJeongbae Seo
351222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) {
352222a13c5STomasz Figa struct clk *clk;
353222a13c5STomasz Figa
354222a13c5STomasz Figa clk = ourhost->clk_bus[src];
355222a13c5STomasz Figa if (IS_ERR(clk))
356222a13c5STomasz Figa continue;
357222a13c5STomasz Figa
358222a13c5STomasz Figa rate = clk_round_rate(clk, 0);
359222a13c5STomasz Figa if (rate < min)
360222a13c5STomasz Figa min = rate;
361222a13c5STomasz Figa }
362222a13c5STomasz Figa
363222a13c5STomasz Figa return min;
364253e0a7cSJeongbae Seo }
365253e0a7cSJeongbae Seo
366253e0a7cSJeongbae Seo /* sdhci_cmu_set_clock - callback on clock change.*/
sdhci_cmu_set_clock(struct sdhci_host * host,unsigned int clock)367253e0a7cSJeongbae Seo static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368253e0a7cSJeongbae Seo {
369253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host);
3702ad0b249SJingoo Han struct device *dev = &ourhost->pdev->dev;
3713119936aSThomas Abraham unsigned long timeout;
3723119936aSThomas Abraham u16 clk = 0;
373cd0cfdd2SMark Brown int ret;
374253e0a7cSJeongbae Seo
3751650d0c7SRussell King host->mmc->actual_clock = 0;
3761650d0c7SRussell King
3777ef2a5e2SJaehoon Chung /* If the clock is going off, set to 0 at clock control register */
3787ef2a5e2SJaehoon Chung if (clock == 0) {
3797ef2a5e2SJaehoon Chung sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380253e0a7cSJeongbae Seo return;
3817ef2a5e2SJaehoon Chung }
382253e0a7cSJeongbae Seo
383253e0a7cSJeongbae Seo sdhci_s3c_set_clock(host, clock);
384253e0a7cSJeongbae Seo
385017210d1SPaul Osmialowski /* Reset SD Clock Enable */
386017210d1SPaul Osmialowski clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387017210d1SPaul Osmialowski clk &= ~SDHCI_CLOCK_CARD_EN;
388017210d1SPaul Osmialowski sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389017210d1SPaul Osmialowski
390cd0cfdd2SMark Brown ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391cd0cfdd2SMark Brown if (ret != 0) {
392cd0cfdd2SMark Brown dev_err(dev, "%s: failed to set clock rate %uHz\n",
393cd0cfdd2SMark Brown mmc_hostname(host->mmc), clock);
394cd0cfdd2SMark Brown return;
395cd0cfdd2SMark Brown }
396253e0a7cSJeongbae Seo
3973119936aSThomas Abraham clk = SDHCI_CLOCK_INT_EN;
3983119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
3993119936aSThomas Abraham
4003119936aSThomas Abraham /* Wait max 20 ms */
4013119936aSThomas Abraham timeout = 20;
4023119936aSThomas Abraham while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
4033119936aSThomas Abraham & SDHCI_CLOCK_INT_STABLE)) {
4043119936aSThomas Abraham if (timeout == 0) {
4052ad0b249SJingoo Han dev_err(dev, "%s: Internal clock never stabilised.\n",
4062ad0b249SJingoo Han mmc_hostname(host->mmc));
4073119936aSThomas Abraham return;
4083119936aSThomas Abraham }
4093119936aSThomas Abraham timeout--;
4103119936aSThomas Abraham mdelay(1);
4113119936aSThomas Abraham }
4123119936aSThomas Abraham
4133119936aSThomas Abraham clk |= SDHCI_CLOCK_CARD_EN;
4143119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415253e0a7cSJeongbae Seo }
416253e0a7cSJeongbae Seo
4170d1bb41aSBen Dooks static struct sdhci_ops sdhci_s3c_ops = {
4180d1bb41aSBen Dooks .get_max_clock = sdhci_s3c_get_max_clk,
4190d1bb41aSBen Dooks .set_clock = sdhci_s3c_set_clock,
420ce5f036bSMarek Szyprowski .get_min_clock = sdhci_s3c_get_min_clock,
4215b7f5eafSMichał Mirosław .set_bus_width = sdhci_set_bus_width,
42203231f9bSRussell King .reset = sdhci_reset,
42396d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling,
4240d1bb41aSBen Dooks };
4250d1bb41aSBen Dooks
426cd1b00ebSThomas Abraham #ifdef CONFIG_OF
sdhci_s3c_parse_dt(struct device * dev,struct sdhci_host * host,struct s3c_sdhci_platdata * pdata)427c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev,
428cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
429cd1b00ebSThomas Abraham {
430cd1b00ebSThomas Abraham struct device_node *node = dev->of_node;
431cd1b00ebSThomas Abraham u32 max_width;
432cd1b00ebSThomas Abraham
433cd1b00ebSThomas Abraham /* if the bus-width property is not specified, assume width as 1 */
434cd1b00ebSThomas Abraham if (of_property_read_u32(node, "bus-width", &max_width))
435cd1b00ebSThomas Abraham max_width = 1;
436cd1b00ebSThomas Abraham pdata->max_width = max_width;
437cd1b00ebSThomas Abraham
438cd1b00ebSThomas Abraham /* get the card detection method */
439ca6b5fe2SRob Herring if (of_property_read_bool(node, "broken-cd")) {
440cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_NONE;
441e19499aeSThomas Abraham return 0;
442cd1b00ebSThomas Abraham }
443cd1b00ebSThomas Abraham
444ca6b5fe2SRob Herring if (of_property_read_bool(node, "non-removable")) {
445cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
446e19499aeSThomas Abraham return 0;
447cd1b00ebSThomas Abraham }
448cd1b00ebSThomas Abraham
44911bc9381SJaehoon Chung if (of_get_named_gpio(node, "cd-gpios", 0))
450e19499aeSThomas Abraham return 0;
451cd1b00ebSThomas Abraham
452b96efccbSTomasz Figa /* assuming internal card detect that will be configured by pinctrl */
453b96efccbSTomasz Figa pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
454cd1b00ebSThomas Abraham return 0;
455cd1b00ebSThomas Abraham }
456cd1b00ebSThomas Abraham #else
sdhci_s3c_parse_dt(struct device * dev,struct sdhci_host * host,struct s3c_sdhci_platdata * pdata)457c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev,
458cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
459cd1b00ebSThomas Abraham {
460cd1b00ebSThomas Abraham return -EINVAL;
461cd1b00ebSThomas Abraham }
462cd1b00ebSThomas Abraham #endif
463cd1b00ebSThomas Abraham
sdhci_s3c_get_driver_data(struct platform_device * pdev)464e614740aSKrzysztof Kozlowski static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
4653119936aSThomas Abraham struct platform_device *pdev)
4663119936aSThomas Abraham {
467cd1b00ebSThomas Abraham #ifdef CONFIG_OF
4680ab53e49SKrzysztof Kozlowski if (pdev->dev.of_node)
469e614740aSKrzysztof Kozlowski return of_device_get_match_data(&pdev->dev);
470cd1b00ebSThomas Abraham #endif
471e614740aSKrzysztof Kozlowski return (const struct sdhci_s3c_drv_data *)
4723119936aSThomas Abraham platform_get_device_id(pdev)->driver_data;
4733119936aSThomas Abraham }
4743119936aSThomas Abraham
sdhci_s3c_probe(struct platform_device * pdev)475c3be1efdSBill Pemberton static int sdhci_s3c_probe(struct platform_device *pdev)
4760d1bb41aSBen Dooks {
4771d4dc338SThomas Abraham struct s3c_sdhci_platdata *pdata;
478e614740aSKrzysztof Kozlowski const struct sdhci_s3c_drv_data *drv_data;
4790d1bb41aSBen Dooks struct device *dev = &pdev->dev;
4800d1bb41aSBen Dooks struct sdhci_host *host;
4810d1bb41aSBen Dooks struct sdhci_s3c *sc;
4820d1bb41aSBen Dooks int ret, irq, ptr, clks;
4830d1bb41aSBen Dooks
484cd1b00ebSThomas Abraham if (!pdev->dev.platform_data && !pdev->dev.of_node) {
4850d1bb41aSBen Dooks dev_err(dev, "no device data specified\n");
4860d1bb41aSBen Dooks return -ENOENT;
4870d1bb41aSBen Dooks }
4880d1bb41aSBen Dooks
4890d1bb41aSBen Dooks irq = platform_get_irq(pdev, 0);
4909a7957d0SStephen Boyd if (irq < 0)
4910d1bb41aSBen Dooks return irq;
4920d1bb41aSBen Dooks
4930d1bb41aSBen Dooks host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
4940d1bb41aSBen Dooks if (IS_ERR(host)) {
4950d1bb41aSBen Dooks dev_err(dev, "sdhci_alloc_host() failed\n");
4960d1bb41aSBen Dooks return PTR_ERR(host);
4970d1bb41aSBen Dooks }
498cd1b00ebSThomas Abraham sc = sdhci_priv(host);
4990d1bb41aSBen Dooks
5001d4dc338SThomas Abraham pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
5011d4dc338SThomas Abraham if (!pdata) {
5021d4dc338SThomas Abraham ret = -ENOMEM;
503b1b8fea9STomasz Figa goto err_pdata_io_clk;
5041d4dc338SThomas Abraham }
505cd1b00ebSThomas Abraham
506cd1b00ebSThomas Abraham if (pdev->dev.of_node) {
507cd1b00ebSThomas Abraham ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
508cd1b00ebSThomas Abraham if (ret)
509b1b8fea9STomasz Figa goto err_pdata_io_clk;
510cd1b00ebSThomas Abraham } else {
5111d4dc338SThomas Abraham memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
512cd1b00ebSThomas Abraham }
5131d4dc338SThomas Abraham
5143119936aSThomas Abraham drv_data = sdhci_s3c_get_driver_data(pdev);
5150d1bb41aSBen Dooks
5160d1bb41aSBen Dooks sc->host = host;
5170d1bb41aSBen Dooks sc->pdev = pdev;
5180d1bb41aSBen Dooks sc->pdata = pdata;
5193ac147faSTomasz Figa sc->cur_clk = -1;
5200d1bb41aSBen Dooks
5210d1bb41aSBen Dooks platform_set_drvdata(pdev, host);
5220d1bb41aSBen Dooks
5233aaf7ba7SJingoo Han sc->clk_io = devm_clk_get(dev, "hsmmc");
5240d1bb41aSBen Dooks if (IS_ERR(sc->clk_io)) {
5250d1bb41aSBen Dooks dev_err(dev, "failed to get io clock\n");
5260d1bb41aSBen Dooks ret = PTR_ERR(sc->clk_io);
527b1b8fea9STomasz Figa goto err_pdata_io_clk;
5280d1bb41aSBen Dooks }
5290d1bb41aSBen Dooks
5300d1bb41aSBen Dooks /* enable the local io clock and keep it running for the moment. */
5310f310a05SThomas Abraham clk_prepare_enable(sc->clk_io);
5320d1bb41aSBen Dooks
5330d1bb41aSBen Dooks for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
5344346b6d9SRajeshwari Shinde char name[14];
5350d1bb41aSBen Dooks
5364346b6d9SRajeshwari Shinde snprintf(name, 14, "mmc_busclk.%d", ptr);
5378f4b78d9STomasz Figa sc->clk_bus[ptr] = devm_clk_get(dev, name);
5388f4b78d9STomasz Figa if (IS_ERR(sc->clk_bus[ptr]))
5390d1bb41aSBen Dooks continue;
5400d1bb41aSBen Dooks
5410d1bb41aSBen Dooks clks++;
5426eb28bdcSTomasz Figa sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
5436eb28bdcSTomasz Figa
5440d1bb41aSBen Dooks dev_info(dev, "clock source %d: %s (%ld Hz)\n",
5456eb28bdcSTomasz Figa ptr, name, sc->clk_rates[ptr]);
5460d1bb41aSBen Dooks }
5470d1bb41aSBen Dooks
5480d1bb41aSBen Dooks if (clks == 0) {
5490d1bb41aSBen Dooks dev_err(dev, "failed to find any bus clocks\n");
5500d1bb41aSBen Dooks ret = -ENOENT;
5510d1bb41aSBen Dooks goto err_no_busclks;
5520d1bb41aSBen Dooks }
5530d1bb41aSBen Dooks
55409938ce8SYangtao Li host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
555a3e2cd7fSThierry Reding if (IS_ERR(host->ioaddr)) {
556a3e2cd7fSThierry Reding ret = PTR_ERR(host->ioaddr);
5570d1bb41aSBen Dooks goto err_req_regs;
5580d1bb41aSBen Dooks }
5590d1bb41aSBen Dooks
5600d1bb41aSBen Dooks /* Ensure we have minimal gpio selected CMD/CLK/Detect */
5610d1bb41aSBen Dooks if (pdata->cfg_gpio)
5620d1bb41aSBen Dooks pdata->cfg_gpio(pdev, pdata->max_width);
5630d1bb41aSBen Dooks
5640d1bb41aSBen Dooks host->hw_name = "samsung-hsmmc";
5650d1bb41aSBen Dooks host->ops = &sdhci_s3c_ops;
5660d1bb41aSBen Dooks host->quirks = 0;
567285e244fSJaehoon Chung host->quirks2 = 0;
5680d1bb41aSBen Dooks host->irq = irq;
5690d1bb41aSBen Dooks
5700d1bb41aSBen Dooks /* Setup quirks for the controller */
571b2e75effSThomas Abraham host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
572a1d56460SMarek Szyprowski host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
5731771059cSRussell King if (drv_data) {
5743119936aSThomas Abraham host->quirks |= drv_data->sdhci_quirks;
5751771059cSRussell King sc->no_divider = drv_data->no_divider;
5761771059cSRussell King }
5770d1bb41aSBen Dooks
5780d1bb41aSBen Dooks #ifndef CONFIG_MMC_SDHCI_S3C_DMA
5790d1bb41aSBen Dooks
5800d1bb41aSBen Dooks /* we currently see overruns on errors, so disable the SDMA
5810d1bb41aSBen Dooks * support as well. */
5820d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
5830d1bb41aSBen Dooks
5840d1bb41aSBen Dooks #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
5850d1bb41aSBen Dooks
5860d1bb41aSBen Dooks /* It seems we do not get an DATA transfer complete on non-busy
5870d1bb41aSBen Dooks * transfers, not sure if this is a problem with this specific
5880d1bb41aSBen Dooks * SDHCI block, or a missing configuration that needs to be set. */
5890d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
5900d1bb41aSBen Dooks
591732f0e31SKyungmin Park /* This host supports the Auto CMD12 */
592732f0e31SKyungmin Park host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
593732f0e31SKyungmin Park
5947199e2b6SJaehoon Chung /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
5957199e2b6SJaehoon Chung host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
5967199e2b6SJaehoon Chung
59717866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
59817866e14SMarek Szyprowski pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
59917866e14SMarek Szyprowski host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
60017866e14SMarek Szyprowski
60117866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
60217866e14SMarek Szyprowski host->mmc->caps = MMC_CAP_NONREMOVABLE;
60317866e14SMarek Szyprowski
6040d22c770SThomas Abraham switch (pdata->max_width) {
6050d22c770SThomas Abraham case 8:
6060d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_8_BIT_DATA;
607df561f66SGustavo A. R. Silva fallthrough;
6080d22c770SThomas Abraham case 4:
6090d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_4_BIT_DATA;
6100d22c770SThomas Abraham break;
6110d22c770SThomas Abraham }
6120d22c770SThomas Abraham
613fa1773ccSSangwook Lee if (pdata->pm_caps)
614fa1773ccSSangwook Lee host->mmc->pm_caps |= pdata->pm_caps;
615fa1773ccSSangwook Lee
6160d1bb41aSBen Dooks host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
6170d1bb41aSBen Dooks SDHCI_QUIRK_32BIT_DMA_SIZE);
6180d1bb41aSBen Dooks
6193fe42e07SHyuk Lee /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
6203fe42e07SHyuk Lee host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
6213fe42e07SHyuk Lee
622253e0a7cSJeongbae Seo /*
623253e0a7cSJeongbae Seo * If controller does not have internal clock divider,
624253e0a7cSJeongbae Seo * we can use overriding functions instead of default.
625253e0a7cSJeongbae Seo */
6261771059cSRussell King if (sc->no_divider) {
627253e0a7cSJeongbae Seo sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
628253e0a7cSJeongbae Seo sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
629253e0a7cSJeongbae Seo sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
630253e0a7cSJeongbae Seo }
631253e0a7cSJeongbae Seo
632b3824f2cSJeongbae Seo /* It supports additional host capabilities if needed */
633b3824f2cSJeongbae Seo if (pdata->host_caps)
634b3824f2cSJeongbae Seo host->mmc->caps |= pdata->host_caps;
635b3824f2cSJeongbae Seo
636c1c4b66dSJaehoon Chung if (pdata->host_caps2)
637c1c4b66dSJaehoon Chung host->mmc->caps2 |= pdata->host_caps2;
638c1c4b66dSJaehoon Chung
6399f4e8151SMark Brown pm_runtime_enable(&pdev->dev);
6409f4e8151SMark Brown pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
6419f4e8151SMark Brown pm_runtime_use_autosuspend(&pdev->dev);
6429f4e8151SMark Brown pm_suspend_ignore_children(&pdev->dev, 1);
6439f4e8151SMark Brown
644f8e3260cSUlf Hansson ret = mmc_of_parse(host->mmc);
645f8e3260cSUlf Hansson if (ret)
646f8e3260cSUlf Hansson goto err_req_regs;
64711bc9381SJaehoon Chung
6480d1bb41aSBen Dooks ret = sdhci_add_host(host);
649fb8617e1SJisheng Zhang if (ret)
6509bda6da7SJulia Lawall goto err_req_regs;
6510d1bb41aSBen Dooks
652162d6f98SRafael J. Wysocki #ifdef CONFIG_PM
6530aa55c23SSeungwon Jeon if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
6540f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io);
6552abeb5c5SChander Kashyap #endif
6560d1bb41aSBen Dooks return 0;
6570d1bb41aSBen Dooks
6580d1bb41aSBen Dooks err_req_regs:
659221414dbSBartlomiej Zolnierkiewicz pm_runtime_disable(&pdev->dev);
660221414dbSBartlomiej Zolnierkiewicz
6610d1bb41aSBen Dooks err_no_busclks:
6620f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io);
6630d1bb41aSBen Dooks
664b1b8fea9STomasz Figa err_pdata_io_clk:
6650d1bb41aSBen Dooks sdhci_free_host(host);
6660d1bb41aSBen Dooks
6670d1bb41aSBen Dooks return ret;
6680d1bb41aSBen Dooks }
6690d1bb41aSBen Dooks
sdhci_s3c_remove(struct platform_device * pdev)670*44417666SYangtao Li static void sdhci_s3c_remove(struct platform_device *pdev)
6710d1bb41aSBen Dooks {
6729d51a6b2SMarek Szyprowski struct sdhci_host *host = platform_get_drvdata(pdev);
6739d51a6b2SMarek Szyprowski struct sdhci_s3c *sc = sdhci_priv(host);
67417866e14SMarek Szyprowski
67517866e14SMarek Szyprowski if (sc->ext_cd_irq)
67617866e14SMarek Szyprowski free_irq(sc->ext_cd_irq, sc);
67717866e14SMarek Szyprowski
678162d6f98SRafael J. Wysocki #ifdef CONFIG_PM
67911bc9381SJaehoon Chung if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
6800f310a05SThomas Abraham clk_prepare_enable(sc->clk_io);
6812abeb5c5SChander Kashyap #endif
6829d51a6b2SMarek Szyprowski sdhci_remove_host(host, 1);
6839d51a6b2SMarek Szyprowski
684387a8cbdSChander Kashyap pm_runtime_dont_use_autosuspend(&pdev->dev);
6859f4e8151SMark Brown pm_runtime_disable(&pdev->dev);
6869f4e8151SMark Brown
6870f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io);
6889d51a6b2SMarek Szyprowski
6899d51a6b2SMarek Szyprowski sdhci_free_host(host);
6900d1bb41aSBen Dooks }
6910d1bb41aSBen Dooks
692d5e9c02cSMark Brown #ifdef CONFIG_PM_SLEEP
sdhci_s3c_suspend(struct device * dev)69329495aa0SManuel Lauss static int sdhci_s3c_suspend(struct device *dev)
6940d1bb41aSBen Dooks {
69529495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev);
6960d1bb41aSBen Dooks
697d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3)
698d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc);
699d38dcad4SAdrian Hunter
70029495aa0SManuel Lauss return sdhci_suspend_host(host);
7010d1bb41aSBen Dooks }
7020d1bb41aSBen Dooks
sdhci_s3c_resume(struct device * dev)70329495aa0SManuel Lauss static int sdhci_s3c_resume(struct device *dev)
7040d1bb41aSBen Dooks {
70529495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev);
7060d1bb41aSBen Dooks
70765d13516SWonil Choi return sdhci_resume_host(host);
7080d1bb41aSBen Dooks }
709d5e9c02cSMark Brown #endif
7100d1bb41aSBen Dooks
711162d6f98SRafael J. Wysocki #ifdef CONFIG_PM
sdhci_s3c_runtime_suspend(struct device * dev)7129f4e8151SMark Brown static int sdhci_s3c_runtime_suspend(struct device *dev)
7139f4e8151SMark Brown {
7149f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev);
7152abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host);
7162abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io;
7172abeb5c5SChander Kashyap int ret;
7189f4e8151SMark Brown
7192abeb5c5SChander Kashyap ret = sdhci_runtime_suspend_host(host);
7202abeb5c5SChander Kashyap
721d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3)
722d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc);
723d38dcad4SAdrian Hunter
7243ac147faSTomasz Figa if (ourhost->cur_clk >= 0)
7250f310a05SThomas Abraham clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
7260f310a05SThomas Abraham clk_disable_unprepare(busclk);
7272abeb5c5SChander Kashyap return ret;
7289f4e8151SMark Brown }
7299f4e8151SMark Brown
sdhci_s3c_runtime_resume(struct device * dev)7309f4e8151SMark Brown static int sdhci_s3c_runtime_resume(struct device *dev)
7319f4e8151SMark Brown {
7329f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev);
7332abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host);
7342abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io;
7352abeb5c5SChander Kashyap int ret;
7369f4e8151SMark Brown
7370f310a05SThomas Abraham clk_prepare_enable(busclk);
7383ac147faSTomasz Figa if (ourhost->cur_clk >= 0)
7390f310a05SThomas Abraham clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
740c6303c5dSBaolin Wang ret = sdhci_runtime_resume_host(host, 0);
7412abeb5c5SChander Kashyap return ret;
7429f4e8151SMark Brown }
7439f4e8151SMark Brown #endif
7449f4e8151SMark Brown
74529495aa0SManuel Lauss static const struct dev_pm_ops sdhci_s3c_pmops = {
746d5e9c02cSMark Brown SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
7479f4e8151SMark Brown SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
7489f4e8151SMark Brown NULL)
74929495aa0SManuel Lauss };
75029495aa0SManuel Lauss
7514d0aa491SKrzysztof Kozlowski static const struct platform_device_id sdhci_s3c_driver_ids[] = {
7523119936aSThomas Abraham {
7533119936aSThomas Abraham .name = "s3c-sdhci",
7543119936aSThomas Abraham .driver_data = (kernel_ulong_t)NULL,
7553119936aSThomas Abraham },
7563119936aSThomas Abraham { }
7573119936aSThomas Abraham };
7583119936aSThomas Abraham MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
7593119936aSThomas Abraham
760cd1b00ebSThomas Abraham #ifdef CONFIG_OF
761e614740aSKrzysztof Kozlowski static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
7623a8e9cadSMarek Szyprowski .no_divider = true,
7633a8e9cadSMarek Szyprowski };
7643a8e9cadSMarek Szyprowski
765cd1b00ebSThomas Abraham static const struct of_device_id sdhci_s3c_dt_match[] = {
766cd1b00ebSThomas Abraham { .compatible = "samsung,s3c6410-sdhci", },
767cd1b00ebSThomas Abraham { .compatible = "samsung,exynos4210-sdhci",
7683a8e9cadSMarek Szyprowski .data = &exynos4_sdhci_drv_data },
769cd1b00ebSThomas Abraham {},
770cd1b00ebSThomas Abraham };
771cd1b00ebSThomas Abraham MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
772cd1b00ebSThomas Abraham #endif
773cd1b00ebSThomas Abraham
7740d1bb41aSBen Dooks static struct platform_driver sdhci_s3c_driver = {
7750d1bb41aSBen Dooks .probe = sdhci_s3c_probe,
776*44417666SYangtao Li .remove_new = sdhci_s3c_remove,
7773119936aSThomas Abraham .id_table = sdhci_s3c_driver_ids,
7780d1bb41aSBen Dooks .driver = {
7790d1bb41aSBen Dooks .name = "s3c-sdhci",
78021b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
781cd1b00ebSThomas Abraham .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
7826b3a194bSUlf Hansson .pm = &sdhci_s3c_pmops,
7830d1bb41aSBen Dooks },
7840d1bb41aSBen Dooks };
7850d1bb41aSBen Dooks
786d1f81a64SAxel Lin module_platform_driver(sdhci_s3c_driver);
7870d1bb41aSBen Dooks
7880d1bb41aSBen Dooks MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
7890d1bb41aSBen Dooks MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
7900d1bb41aSBen Dooks MODULE_LICENSE("GPL v2");
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