| /openbmc/openbmc/meta-openpower/recipes-bsp/ekb/ |
| H A D | ekb.inc | 10 chips/p10/procedures/xml/attribute_info/p10_bars_attributes.xml \
11 chips/p10/procedures/xml/attribute_info/p10_chip_ec_attributes.xml \
12 chips/p10/procedures/xml/attribute_info/p10_clock_attributes.xml \
13 chips/p10/procedures/xml/attribute_info/p10_freq_attributes.xml \
14 chips/p10/procedures/xml/attribute_info/p10_hcode_image_build_attributes.xml \
15 chips/p10/procedures/xml/attribute_info/p10_ipl_attributes.xml \
16 chips/p10/procedures/xml/attribute_info/p10_ipl_customize_attributes.xml \
17 chips/p10/procedures/xml/attribute_info/p10_memory_bars_attributes.xml \
18 chips/p10/procedures/xml/attribute_info/p10_nest_attributes.xml \
19 chips/p10/procedures/xml/attribute_info/p10_pervasive_attributes.xml \
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| /openbmc/u-boot/drivers/mtd/spi/ |
| H A D | Kconfig | 10 SPI flash driver which knows how to probe most chips
101 Add support for various Atmel SPI flash chips (AT45xxx and AT25xxx)
106 Add support for various EON SPI flash chips (EN25xxx)
111 Add support for various GigaDevice SPI flash chips (GD25xxx)
116 Add support for various ISSI SPI flash chips (ISxxx)
121 Add support for various Macronix SPI flash chips (MX25Lxxx)
126 Add support for various Spansion SPI flash chips (S25FLxxx)
131 Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx)
136 Add support for various SST SPI flash chips (SST25xxx)
141 Add support for various Winbond SPI flash chips (W25xxx)
[all …]
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| H A D | sf_dataflash.c | 62 * newer chips report JEDEC manufacturer and device IDs; chip
242 * the peak rate available. Some chips support commands with in spi_dataflash_read()
466 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
478 * These newer chips also support 128-byte security registers (with
516 * we use here. Supporting some chips might require using it. in jedec_probe()
519 * That's not an error; only rev C and newer chips handle it, and in jedec_probe()
520 * only Atmel sells these chips. in jedec_probe()
561 * Treat other chips as errors ... we won't know the right page in jedec_probe()
570 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
617 * Older chips support only legacy commands, identifing in spi_dataflash_probe()
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| /openbmc/openpower-hw-diags/ |
| H A D | README.md | 4 (processor chips, memory chips, I/O chips, system memory, etc.), POWER Systems
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| /openbmc/openpower-hw-diags/analyzer/plugins/ |
| H A D | p10-tod-plugins.cpp | 44 /** The MDMT chips at fault (only one per topology). */
47 /** All chips with internal path faults. */
50 /** The chips sourcing the clocks to non-MDMT chips with faults. */
87 * @return The list of all chips with internal faults.
114 * @return The list of all chips sourcing the clocks for the non-MDMT chips
254 // The slave path selects are sourced from other processor chips. in collectTodFaultData()
329 // from the non-MDMT chips. In which case, we will want to call out all in tod_step_check_fault()
330 // of the chips sourcing those step check errors (not the chips reporting in tod_step_check_fault()
332 // - If no other errors found, callout any chips reporting internal step in tod_step_check_fault()
364 // Callout all chips with network errors (no guard to avoid fatal in tod_step_check_fault()
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| /openbmc/openpower-hw-diags/test/ |
| H A D | test-pdbg-dts.cpp | 244 std::vector<libhei::Chip> chips; in TEST() local
245 getActiveChips(chips); in TEST()
247 trace::inf("chips size: %u", chips.size()); in TEST()
248 EXPECT_EQ(2, chips.size()); in TEST()
278 std::vector<libhei::Chip> chips; in TEST()
279 getActiveChips(chips); in TEST()
281 // In total there should be 14 chips with 2 processors, 7 OCMBs on proc0, in TEST()
284 trace::inf("chips size: %u", chips.size()); in TEST()
285 EXPECT_EQ(14, chips.size()); in TEST()
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| /openbmc/openbmc/meta-openpower/recipes-phosphor/logging/ |
| H A D | openpower-hw-diags_git.bb | 5 hardware (processor chips, memory chips, I/O chips, system memory, etc.), \
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| H A D | openpower-libhei_git.bb | 5 by POWER Systems chip (processor chips, memory chips, etc.)."
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| /openbmc/openpower-hw-diags/analyzer/ |
| H A D | analyzer_main.cpp | 20 * @param o_chips The returned list of active chips.
110 // Initialize the isolator and get all of the chips to be analyzed. in analyzeHardware()
112 std::vector<libhei::Chip> chips; in analyzeHardware() local
113 initializeIsolator(chips); in analyzeHardware()
116 trace::inf("Isolating errors: # of chips=%u", chips.size()); in analyzeHardware()
118 libhei::isolate(chips, isoData); in analyzeHardware()
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| /openbmc/u-boot/drivers/mtd/ |
| H A D | Kconfig | 11 flash, RAM and similar chips, often used for solid state file
78 This enables access to Altera EPCQ/EPCS flash chips using the
88 chips through PIC32 Non-Volatile-Memory Controller.
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| /openbmc/docs/designs/oem/google/ |
| H A D | root_of_trust.md | 12 Trust (RoT) chips. Google needs APIs that are not in the Redfish standard yet.
13 There are working groups dedicated to bring RoT chips support to the Redfish
20 At Google, we rely on communicating with RoT chips using a variety of transport
102 difference between any TPM and Google's RoT chips.
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| /openbmc/u-boot/doc/device-tree-bindings/mtd/spi/ |
| H A D | spi-flash.txt | 1 * MTD SPI driver for serial flash chips
9 drivers/mtd/spi/spi_flash_ids.c for the list of supported chips.
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| /openbmc/openbmc/meta-ibm/recipes-phosphor/sensors/ |
| H A D | phosphor-hwmon_%.bbappend | 7 CHIPS:witherspoon = " \
20 CHIPS:p10bmc = " \
35 ITEMS = "${@compose_list(d, 'ITEMSFMT', 'CHIPS')}"
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| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | psc.c | 20 * DaVinci chips may include two separate power domains: "Always On" and "DSP".
21 * Chips without a DSP generally have only one domain.
28 * hardware such as VICP. In some chips, the "DSP" domain is not always on.
120 /* Not all DaVinci chips have a DSP power domain. */
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| /openbmc/openbmc/meta-ibm/meta-romulus/recipes-phosphor/sensors/ |
| H A D | phosphor-hwmon_%.bbappend | 5 CHIPS = " \
11 ITEMS = "${@compose_list(d, 'ITEMSFMT', 'CHIPS')}"
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| /openbmc/u-boot/doc/device-tree-bindings/mtd/ |
| H A D | mtd-physmap.txt | 3 Flash chips (Memory Technology Devices) are often used for solid state
11 non-identical chips can be described in one node.
13 device width times the number of interleaved chips.
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| /openbmc/u-boot/drivers/i2c/muxes/ |
| H A D | pca954x.c | 39 static const struct chip_desc chips[] = { variable
75 const struct chip_desc *chip = &chips[dev_get_driver_data(mux)]; in pca954x_select()
102 const struct chip_desc *chip = &chips[dev_get_driver_data(dev)]; in pca954x_ofdata_to_platdata()
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| /openbmc/openpower-hw-diags/util/ |
| H A D | pdbg.hpp | 127 * @brief Returns the list of all active chips in the system.
128 * @param o_chips The returned list of chips.
133 * @brief Returns the list of all active processor chips in the system.
134 * @param o_chips The returned list of chips.
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| /openbmc/openpower-proc-control/procedures/common/ |
| H A D | cfam_reset.cpp | 60 // Put chips into reset in cfamReset()
67 // Take chips out of reset in cfamReset()
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| /openbmc/u-boot/drivers/misc/ |
| H A D | Kconfig | 32 Support the FSI master present in the ASPEED system on chips.
160 in the Nuvoton Super IO chips on X86 platforms.
240 legacy UART or other devices in the Winbond Super IO chips
305 EEPROM chips that implement "address overflow" are ones
309 byte chips.
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| /openbmc/u-boot/arch/mips/mach-mt7620/ |
| H A D | Kconfig | 103 Use DDR chips with 8bit width
109 Use DDR chips with 16bit width
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| /openbmc/qemu/include/hw/ssi/ |
| H A D | npcm7xx_fiu.h | 44 * @cs_count: Number of flash chips that may be connected to this module.
46 * @cs_lines: GPIO lines that may be wired to flash chips.
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_bbt.c | 256 * @chip: read the table for a specific chip, -1 read all chips; applies only if
259 * Read the bad block table for all chips starting at a given page. We assume
377 * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page
383 * Read the bad block table(s) for all chips starting at a given page. We
446 * @chip: create the table for a specific chip, -1 read all chips; applies only
473 pr_warn("create_bbt(): chipnr (%d) > available chips (%d)\n", in create_bbt()
525 int i, chips; in search_bbt() local
542 chips = this->numchips; in search_bbt()
546 chips = 1; in search_bbt()
550 for (i = 0; i < chips; i++) { in search_bbt()
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | Kconfig | 189 chips are from NXP and TI.
328 Now, max 24 bits chips and PCA953X compatible chips are
351 Now, max 24 bits chips and PCA953X compatible chips are
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 72 many AT91 (ARM) chips. This driver can be used to access
140 This driver can be used to access the SPI NOR flash chips on
244 used to access the SPI NOR flash chips on platforms embedding
275 be used to access SPI chips on platforms embedding this
403 (McSPI). This driver be used to access SPI chips on platforms
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