1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2601fbec7SMasahiro Yamada /*
3601fbec7SMasahiro Yamada * Power and Sleep Controller (PSC) functions.
4601fbec7SMasahiro Yamada *
5601fbec7SMasahiro Yamada * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6601fbec7SMasahiro Yamada * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
7601fbec7SMasahiro Yamada * Copyright (C) 2004 Texas Instruments.
8601fbec7SMasahiro Yamada */
9601fbec7SMasahiro Yamada
10601fbec7SMasahiro Yamada #include <common.h>
11601fbec7SMasahiro Yamada #include <asm/arch/hardware.h>
12601fbec7SMasahiro Yamada #include <asm/io.h>
13601fbec7SMasahiro Yamada
14601fbec7SMasahiro Yamada /*
15601fbec7SMasahiro Yamada * The PSC manages three inputs to a "module" which may be a peripheral or
16601fbec7SMasahiro Yamada * CPU. Those inputs are the module's: clock; reset signal; and sometimes
17601fbec7SMasahiro Yamada * its power domain. For our purposes, we only care whether clock and power
18601fbec7SMasahiro Yamada * are active, and the module is out of reset.
19601fbec7SMasahiro Yamada *
20601fbec7SMasahiro Yamada * DaVinci chips may include two separate power domains: "Always On" and "DSP".
21601fbec7SMasahiro Yamada * Chips without a DSP generally have only one domain.
22601fbec7SMasahiro Yamada *
23601fbec7SMasahiro Yamada * The "Always On" power domain is always on when the chip is on, and is
24601fbec7SMasahiro Yamada * powered by the VDD pins (on DM644X). The majority of DaVinci modules
25601fbec7SMasahiro Yamada * lie within the "Always On" power domain.
26601fbec7SMasahiro Yamada *
27601fbec7SMasahiro Yamada * A separate domain called the "DSP" domain houses the C64x+ and other video
28601fbec7SMasahiro Yamada * hardware such as VICP. In some chips, the "DSP" domain is not always on.
29601fbec7SMasahiro Yamada * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
30601fbec7SMasahiro Yamada */
31601fbec7SMasahiro Yamada
32601fbec7SMasahiro Yamada /* Works on Always On power domain only (no PD argument) */
lpsc_transition(unsigned int id,unsigned int state)33601fbec7SMasahiro Yamada static void lpsc_transition(unsigned int id, unsigned int state)
34601fbec7SMasahiro Yamada {
35601fbec7SMasahiro Yamada dv_reg_p mdstat, mdctl, ptstat, ptcmd;
36601fbec7SMasahiro Yamada #ifdef CONFIG_SOC_DA8XX
37601fbec7SMasahiro Yamada struct davinci_psc_regs *psc_regs;
38601fbec7SMasahiro Yamada #endif
39601fbec7SMasahiro Yamada
40601fbec7SMasahiro Yamada #ifndef CONFIG_SOC_DA8XX
41601fbec7SMasahiro Yamada if (id >= DAVINCI_LPSC_GEM)
42601fbec7SMasahiro Yamada return; /* Don't work on DSP Power Domain */
43601fbec7SMasahiro Yamada
44601fbec7SMasahiro Yamada mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
45601fbec7SMasahiro Yamada mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
46601fbec7SMasahiro Yamada ptstat = REG_P(PSC_PTSTAT);
47601fbec7SMasahiro Yamada ptcmd = REG_P(PSC_PTCMD);
48601fbec7SMasahiro Yamada #else
49601fbec7SMasahiro Yamada if (id < DAVINCI_LPSC_PSC1_BASE) {
50601fbec7SMasahiro Yamada if (id >= PSC_PSC0_MODULE_ID_CNT)
51601fbec7SMasahiro Yamada return;
52601fbec7SMasahiro Yamada psc_regs = davinci_psc0_regs;
53601fbec7SMasahiro Yamada mdstat = &psc_regs->psc0.mdstat[id];
54601fbec7SMasahiro Yamada mdctl = &psc_regs->psc0.mdctl[id];
55601fbec7SMasahiro Yamada } else {
56601fbec7SMasahiro Yamada id -= DAVINCI_LPSC_PSC1_BASE;
57601fbec7SMasahiro Yamada if (id >= PSC_PSC1_MODULE_ID_CNT)
58601fbec7SMasahiro Yamada return;
59601fbec7SMasahiro Yamada psc_regs = davinci_psc1_regs;
60601fbec7SMasahiro Yamada mdstat = &psc_regs->psc1.mdstat[id];
61601fbec7SMasahiro Yamada mdctl = &psc_regs->psc1.mdctl[id];
62601fbec7SMasahiro Yamada }
63601fbec7SMasahiro Yamada ptstat = &psc_regs->ptstat;
64601fbec7SMasahiro Yamada ptcmd = &psc_regs->ptcmd;
65601fbec7SMasahiro Yamada #endif
66601fbec7SMasahiro Yamada
67601fbec7SMasahiro Yamada while (readl(ptstat) & 0x01)
68601fbec7SMasahiro Yamada continue;
69601fbec7SMasahiro Yamada
70601fbec7SMasahiro Yamada if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
71601fbec7SMasahiro Yamada return; /* Already in that state */
72601fbec7SMasahiro Yamada
73601fbec7SMasahiro Yamada writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
74601fbec7SMasahiro Yamada
75601fbec7SMasahiro Yamada switch (id) {
76601fbec7SMasahiro Yamada #ifdef CONFIG_SOC_DM644X
77601fbec7SMasahiro Yamada /* Special treatment for some modules as for sprue14 p.7.4.2 */
78601fbec7SMasahiro Yamada case DAVINCI_LPSC_VPSSSLV:
79601fbec7SMasahiro Yamada case DAVINCI_LPSC_EMAC:
80601fbec7SMasahiro Yamada case DAVINCI_LPSC_EMAC_WRAPPER:
81601fbec7SMasahiro Yamada case DAVINCI_LPSC_MDIO:
82601fbec7SMasahiro Yamada case DAVINCI_LPSC_USB:
83601fbec7SMasahiro Yamada case DAVINCI_LPSC_ATA:
84601fbec7SMasahiro Yamada case DAVINCI_LPSC_VLYNQ:
85601fbec7SMasahiro Yamada case DAVINCI_LPSC_UHPI:
86601fbec7SMasahiro Yamada case DAVINCI_LPSC_DDR_EMIF:
87601fbec7SMasahiro Yamada case DAVINCI_LPSC_AEMIF:
88601fbec7SMasahiro Yamada case DAVINCI_LPSC_MMC_SD:
89601fbec7SMasahiro Yamada case DAVINCI_LPSC_MEMSTICK:
90601fbec7SMasahiro Yamada case DAVINCI_LPSC_McBSP:
91601fbec7SMasahiro Yamada case DAVINCI_LPSC_GPIO:
92601fbec7SMasahiro Yamada writel(readl(mdctl) | 0x200, mdctl);
93601fbec7SMasahiro Yamada break;
94601fbec7SMasahiro Yamada #endif
95601fbec7SMasahiro Yamada }
96601fbec7SMasahiro Yamada
97601fbec7SMasahiro Yamada writel(0x01, ptcmd);
98601fbec7SMasahiro Yamada
99601fbec7SMasahiro Yamada while (readl(ptstat) & 0x01)
100601fbec7SMasahiro Yamada continue;
101601fbec7SMasahiro Yamada while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
102601fbec7SMasahiro Yamada continue;
103601fbec7SMasahiro Yamada }
104601fbec7SMasahiro Yamada
lpsc_on(unsigned int id)105601fbec7SMasahiro Yamada void lpsc_on(unsigned int id)
106601fbec7SMasahiro Yamada {
107601fbec7SMasahiro Yamada lpsc_transition(id, 0x03);
108601fbec7SMasahiro Yamada }
109601fbec7SMasahiro Yamada
lpsc_syncreset(unsigned int id)110601fbec7SMasahiro Yamada void lpsc_syncreset(unsigned int id)
111601fbec7SMasahiro Yamada {
112601fbec7SMasahiro Yamada lpsc_transition(id, 0x01);
113601fbec7SMasahiro Yamada }
114601fbec7SMasahiro Yamada
lpsc_disable(unsigned int id)115601fbec7SMasahiro Yamada void lpsc_disable(unsigned int id)
116601fbec7SMasahiro Yamada {
117601fbec7SMasahiro Yamada lpsc_transition(id, 0x0);
118601fbec7SMasahiro Yamada }
119601fbec7SMasahiro Yamada
120601fbec7SMasahiro Yamada /* Not all DaVinci chips have a DSP power domain. */
121601fbec7SMasahiro Yamada #ifdef CONFIG_SOC_DM644X
122601fbec7SMasahiro Yamada
123601fbec7SMasahiro Yamada /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
124601fbec7SMasahiro Yamada #if !defined(CONFIG_SYS_USE_DSPLINK)
dsp_on(void)125601fbec7SMasahiro Yamada void dsp_on(void)
126601fbec7SMasahiro Yamada {
127601fbec7SMasahiro Yamada int i;
128601fbec7SMasahiro Yamada
129601fbec7SMasahiro Yamada if (REG(PSC_PDSTAT1) & 0x1f)
130601fbec7SMasahiro Yamada return; /* Already on */
131601fbec7SMasahiro Yamada
132601fbec7SMasahiro Yamada REG(PSC_GBLCTL) |= 0x01;
133601fbec7SMasahiro Yamada REG(PSC_PDCTL1) |= 0x01;
134601fbec7SMasahiro Yamada REG(PSC_PDCTL1) &= ~0x100;
135601fbec7SMasahiro Yamada REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
136601fbec7SMasahiro Yamada REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
137601fbec7SMasahiro Yamada REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
138601fbec7SMasahiro Yamada REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
139601fbec7SMasahiro Yamada REG(PSC_PTCMD) = 0x02;
140601fbec7SMasahiro Yamada
141601fbec7SMasahiro Yamada for (i = 0; i < 100; i++) {
142601fbec7SMasahiro Yamada if (REG(PSC_EPCPR) & 0x02)
143601fbec7SMasahiro Yamada break;
144601fbec7SMasahiro Yamada }
145601fbec7SMasahiro Yamada
146601fbec7SMasahiro Yamada REG(PSC_CHP_SHRTSW) = 0x01;
147601fbec7SMasahiro Yamada REG(PSC_PDCTL1) |= 0x100;
148601fbec7SMasahiro Yamada REG(PSC_EPCCR) = 0x02;
149601fbec7SMasahiro Yamada
150601fbec7SMasahiro Yamada for (i = 0; i < 100; i++) {
151601fbec7SMasahiro Yamada if (!(REG(PSC_PTSTAT) & 0x02))
152601fbec7SMasahiro Yamada break;
153601fbec7SMasahiro Yamada }
154601fbec7SMasahiro Yamada
155601fbec7SMasahiro Yamada REG(PSC_GBLCTL) &= ~0x1f;
156601fbec7SMasahiro Yamada }
157601fbec7SMasahiro Yamada #endif /* CONFIG_SYS_USE_DSPLINK */
158601fbec7SMasahiro Yamada
159601fbec7SMasahiro Yamada #endif /* have a DSP */
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