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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D1034 # Test case for qcow2 metadata cache size specification
44 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
49 $QEMU_IO -c 'write -P 42 0 64k' "$TEST_IMG" | _filter_qemu_io
56 $QEMU_IO -c "open -o cache-size=1.25M,l2-cache-size=1M,refcount-cache-size=0.25M $TEST_IMG" \
58 # l2-cache-size may not exceed cache-size
59 $QEMU_IO -c "open -o cache-size=1M,l2-cache-size=2M $TEST_IMG" 2>&1 \
61 # refcount-cache-size may not exceed cache-size
62 $QEMU_IO -c "open -o cache-size=1M,refcount-cache-size=2M $TEST_IMG" 2>&1 \
64 # 0 should be a valid size (e.g. for enforcing the minimum), so this should not
66 $QEMU_IO -c "open -o cache-size=0,l2-cache-size=0,refcount-cache-size=0 $TEST_IMG" \
[all …]
H A D103.out2 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=65536
8 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
9 qemu-io: can't open device TEST_DIR/t.IMGFMT: l2-cache-size may not exceed cache-size
10 qemu-io: can't open device TEST_DIR/t.IMGFMT: refcount-cache-size may not exceed cache-size
11 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
12 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
13 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
14 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
33 === Testing minimal L2 cache and COW ===
H A D026.out.nocache4 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
9 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
14 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
21 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
[all …]
H A D026.out4 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
9 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
14 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
21 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
[all …]
H A D137.out2 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864
18 qemu-io: Parameter 'lazy-refcounts' expects 'on' or 'off'
19 qemu-io: cache-size, l2-cache-size and refcount-cache-size may not be set at the same time
20 qemu-io: l2-cache-size may not exceed cache-size
21 qemu-io: refcount-cache-size may not exceed cache-size
22 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
23 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
24 qemu-io: Refcount cache size too big
25 qemu-io: Conflicting values for qcow2 options 'overlap-check' ('constant') and 'overlap-check.templ…
26 qemu-io: Unsupported value 'blubb' for qcow2 option 'overlap-check'. Allowed are any of the followi…
[all …]
H A D13744 # We are going to use lazy-refcounts
56 -c "reopen -o lazy-refcounts=on,pass-discard-request=on" \
57 -c "reopen -o lazy-refcounts=off,pass-discard-request=off" \
58 -c "reopen -o pass-discard-snapshot=on,pass-discard-other=on" \
59 -c "reopen -o pass-discard-snapshot=off,pass-discard-other=off" \
60 -c "reopen -o overlap-check=all" \
61 -c "reopen -o overlap-check=none" \
62 -c "reopen -o overlap-check=cached" \
63 -c "reopen -o overlap-check=constant" \
64 -c "reopen -o overlap-check.template=all" \
[all …]
H A D191.out5 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=67108864
6 Formatting 'TEST_DIR/t.IMGFMT.mid', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base ba…
7 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.mid backing…
8 Formatting 'TEST_DIR/t.IMGFMT.ovl2', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.mid ba…
19 { 'execute': 'block-commit',
20 'arguments': { 'job-id': 'commit0',
111 { 'execute': 'query-named-block-nodes' }
119 "backing-image": {
120 "virtual-size": 67108864,
122 "cluster-size": 65536,
[all …]
/openbmc/qemu/docs/
H A Dqcow2-cache.txt1 qcow2 L2/refcount cache configuration
3 Copyright (C) 2015, 2018-2020 Igalia, S.L.
7 later. See the COPYING file in the top-level directory.
10 ------------
12 performance significantly. However, setting the right cache sizes is
18 Please refer to the docs/interop/qcow2.rst file for an in-depth
23 --------
24 A qcow2 file is organized in units of constant size called clusters.
26 The cluster size is configurable, but it must be a power of two and
30 The 'qemu-img create' command supports specifying the size using the
[all …]
H A Dxbzrle.txt5 of VM downtime and the total live-migration time of Virtual machines.
15 be stored on the source. Those pages are stored in a dedicated cache
17 The larger the cache size the better the chances are that the page has already
18 been stored in the cache.
19 A small cache size will result in high cache miss rate.
20 Cache size can be changed before and during migration.
45 retrieving the old page content from the cache (default size of 64MB). The
55 XBZRLE has a sustained bandwidth of 2-2.5 GB/s for typical workloads making it
56 ideal for in-line, real-time encoding such as is needed for live-migration.
74 Cache update strategy
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/openbmc/qemu/include/exec/
H A Dmemory_ldst_cached.h.inc20 #define ADDRESS_SPACE_LD_CACHED(size) \
21 glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached))
22 #define ADDRESS_SPACE_LD_CACHED_SLOW(size) \
23 glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached_slow))
24 #define LD_P(size) \
25 glue(glue(ld, size), glue(ENDIANNESS, _p))
27 static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
30 assert(addr < cache->len && 2 <= cache->len - addr);
31 fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
32 if (likely(cache->ptr)) {
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 /* Cache maintenance operation registers */
47 INVALIDATE_POU, /* i-cache invalidate by address */
48 INVALIDATE_POC, /* d-cache invalidate by address */
49 INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
50 FLUSH_POU, /* d-cache clean by address to the PoU */
51 FLUSH_POC, /* d-cache clean by address to the PoC */
52 FLUSH_SET_WAY, /* d-cache clean by sets/ways */
53 FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * Flush the whole D-cache.
21 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
23 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
32 mov r10, #0 @ start clean at cache level 0
34 add r2, r10, r10, lsr #1 @ work out 3x current cache level
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
36 and r1, r1, #7 @ mask of the bits for current cache only
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dcache-uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
14 #include "cache-uniphier.h"
19 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
21 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
22 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
30 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
35 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
51 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
[all …]
/openbmc/u-boot/include/
H A Dmemalign.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
14 #include <asm/cache.h>
21 * the cache before and after a read and/or write operation is required for
29 * 2) The size of the aligned portion of the array is a multiple of the minimum
62 * Note that the size parameter is the number of array elements to allocate,
66 * of a function scoped static buffer. It can not be used to create a cache
69 #define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
71 #define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ argument
72 char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \
[all …]
/openbmc/u-boot/arch/nds32/include/asm/
H A Dcache.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* cache */
33 /* I-cache sets (# of cache lines) per way */
35 /* I-cache ways */
39 /* D-cache sets (# of cache lines) per way */
41 /* D-cache ways */
45 /* I-cache line size */
48 /* D-cache line size */
53 * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
55 * specified an alternate cache line size.
/openbmc/qemu/migration/
H A Dpage_cache.c2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
23 /* the page in cache will not be replaced in two cycles */
45 PageCache *cache; in cache_init() local
48 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
49 "is smaller than one target page size"); in cache_init()
55 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
61 cache = g_try_malloc(sizeof(*cache)); in cache_init()
[all …]
H A Dpage_cache.h2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
11 * See the COPYING file in the top-level directory.
18 /* Page cache for storing guest pages */
22 * cache_init: Initialize the page cache
25 * Returns new allocated cache or NULL on error
27 * @cache_size: cache size in bytes
28 * @page_size: cache page size
33 * cache_fini: free all cache resources
34 * @cache pointer to the PageCache struct
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/
H A D0010-Make-RSS-and-MHU-sizes-compile-time-definitions-user.patch4 Subject: [PATCH 10/12] Make RSE and MHU sizes compile-time definitions
5 user-configurable
8 cache variables that users can configure to change the size of the RSE
11 Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TS/trusted-services/+/31178/1]
12 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
13 Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
14 ---
15 platform/providers/arm/corstone1000/platform.cmake | 6 ++++--
16 1 file changed, 4 insertions(+), 2 deletions(-)
18 diff --git a/platform/providers/arm/corstone1000/platform.cmake b/platform/providers/arm/corstone10…
[all …]
/openbmc/u-boot/arch/mips/lib/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
40 gd->arch.l2_line_size = mips_cm_l2_line_size(); in probe_l2()
46 gd->arch.l2_line_size = sl ? (2 << sl) : 0; in probe_l2()
61 gd->arch.l1i_line_size = il ? (2 << il) : 0; in mips_cache_probe()
62 gd->arch.l1d_line_size = dl ? (2 << dl) : 0; in mips_cache_probe()
70 return gd->arch.l1i_line_size; in icache_line_size()
79 return gd->arch.l1d_line_size; in dcache_line_size()
88 return gd->arch.l2_line_size; in scache_line_size()
95 const void *addr = (const void *)(start & ~(lsize - 1)); \
96 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
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/openbmc/qemu/util/
H A Dcacheflush.c5 * See the COPYING file in the top-level directory.
12 #include "qemu/host-utils.h"
22 * Operating system specific cache detection mechanisms.
30 DWORD size = 0; in sys_cache_info() local
35 * Check for the required buffer size first. Note that if the zero in sys_cache_info()
36 * size we use for the probe results in success, then there is no in sys_cache_info()
39 success = GetLogicalProcessorInformation(0, &size); in sys_cache_info()
44 n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); in sys_cache_info()
45 size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); in sys_cache_info()
47 if (!GetLogicalProcessorInformation(buf, &size)) { in sys_cache_info()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache.S1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <asm-offsets.h>
18 * flush or invalidate one level cache.
20 * x0: cache level
27 msr csselr_el1, x12 /* select cache level */
30 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
31 add x2, x2, #4 /* x2 <- log2(cache line size) */
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
36 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
37 /* x12 <- cache level << 1 */
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dmrccache.h1 /* SPDX-License-Identifier: GPL-2.0+ */
18 u32 data_size; /* Size of the 'data' field */
21 u8 data[0]; /* Variable size, platform/run time dependent */
33 * mrccache_find_current() - find the latest MRC cache record
35 * This searches the MRC cache region looking for the latest record to use
38 * @entry: Position and size of MRC cache in SPI flash
44 * mrccache_update() - update the MRC cache with a new record
46 * This writes a new record to the end of the MRC cache region. If the new
50 * @entry: Position and size of MRC cache in SPI flash
52 * @return 0 if updated, -EEXIST if the record is the same as the latest
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
49 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_cpu()
50 while (off != -FDT_ERR_NOTFOUND) { in ft_fixup_cpu()
68 enable_method = "fsl,brr-holdoff"; in ft_fixup_cpu()
71 enable_method = "fsl,eebpcr-holdoff"; in ft_fixup_cpu()
74 /* Cores out of reset and in a spin-loop */ in ft_fixup_cpu()
75 enable_method = "spin-table"; in ft_fixup_cpu()
77 fdt_setprop(blob, off, "cpu-release-addr", in ft_fixup_cpu()
81 fdt_setprop_string(blob, off, "enable-method", in ft_fixup_cpu()
[all …]
/openbmc/qemu/target/sparc/
H A Dldst_helper.c4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
27 #include "exec/page-protection.h"
29 #include "accel/tcg/cpu-ldst.h"
32 #include "user/page-protection.h"
70 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
77 /* Calculates TSB pointer value for fault page size
79 * UA2005 holds the page size configuration in mmu_ctx registers */
87 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
88 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
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