1 /* SPDX-License-Identifier: GPL-2.0+ */
10  * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
14 #include <asm/cache.h>
21  * the cache before and after a read and/or write operation is required for
29  * 2) The size of the aligned portion of the array is a multiple of the minimum
62  * Note that the size parameter is the number of array elements to allocate,
66  * of a function scoped static buffer.  It can not be used to create a cache
69 #define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
71 #define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad)		\  argument
72 	char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align)  \
73 		      + (align - 1)];					\
76 #define ALLOC_ALIGN_BUFFER(type, name, size, align)		\  argument
77 	ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
78 #define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad)		\  argument
79 	ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
80 #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\  argument
81 	ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
88 #define DEFINE_ALIGN_BUFFER(type, name, size, align)			\  argument
89 	static char __##name[ALIGN(size * sizeof(type), align)]	\
93 #define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)			\  argument
94 	DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
97  * malloc_cache_aligned() - allocate a memory region aligned to cache line size
99  * This allocates memory at a cache-line boundary. The amount allocated may
101  * cache-line size. This ensured that subsequent cache operations on this
104  * @size:	Minimum number of bytes to allocate
109 static inline void *malloc_cache_aligned(size_t size)  in malloc_cache_aligned()  argument
111 	return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN));  in malloc_cache_aligned()