util/cacheflush: Avoid possible redundant dcache flush on Darwin

<libkern/OSCacheControl.h> describes sys_icache_invalidate() as
"equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)",

util/cacheflush: Avoid possible redundant dcache flush on Darwin

<libkern/OSCacheControl.h> describes sys_icache_invalidate() as
"equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)",
having kCacheFunctionPrepareForExecution defined as:

/* Prepare memory for execution. This should be called
* after writing machine instructions to memory, before
* executing them. It syncs the dcache and icache. [...]
*/

Since the dcache is also sync'd, we can avoid the sys_dcache_flush()
call when both rx/rw pointers are equal.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20230605195911.96033-1-philmd@linaro.org>

show more ...

util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin

Per the cache(3) man page, sys_icache_invalidate() and
sys_dcache_flush() are declared in <libkern/OSCacheControl.h>.

Signed-off-

util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin

Per the cache(3) man page, sys_icache_invalidate() and
sys_dcache_flush() are declared in <libkern/OSCacheControl.h>.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230605175647.88395-2-philmd@linaro.org>

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util/cacheflush: fix cache on windows-arm64

ctr_el0 access is privileged on this platform and fails as an illegal
instruction.

Windows does not offer a way to flush data cache from userspace, and
o

util/cacheflush: fix cache on windows-arm64

ctr_el0 access is privileged on this platform and fails as an illegal
instruction.

Windows does not offer a way to flush data cache from userspace, and
only FlushInstructionCache is available in Windows API.

The generic implementation of flush_idcache_range uses,
__builtin___clear_cache, which already use the FlushInstructionCache
function. So we rely on that.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230221153006.20300-2-pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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util/cacheflush: Optimize flushing when ppc host has coherent icache

On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates
that we can use a simplified 3 instruction flush sequence.

Signed-

util/cacheflush: Optimize flushing when ppc host has coherent icache

On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates
that we can use a simplified 3 instruction flush sequence.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220519141131.29839-1-npiggin@gmail.com>
[rth: update after merging cacheflush.c and cacheinfo.c]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org>

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util/cacheflush: Merge aarch64 ctr_el0 usage

Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range,
use the pre-computed line sizes from the global variables.
Use CONFIG_DARWIN in prefere

util/cacheflush: Merge aarch64 ctr_el0 usage

Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range,
use the pre-computed line sizes from the global variables.
Use CONFIG_DARWIN in preference to __APPLE__.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org>

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util: Merge cacheflush.c and cacheinfo.c

Combine the two files into cacheflush.c. There's a couple of bits
that would be helpful to share between the two, and combining them
seems better than expor

util: Merge cacheflush.c and cacheinfo.c

Combine the two files into cacheflush.c. There's a couple of bits
that would be helpful to share between the two, and combining them
seems better than exporting the bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org>

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include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h

The qemu_icache_linesize, qemu_icache_linesize_log,
qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not
used in m

include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h

The qemu_icache_linesize, qemu_icache_linesize_log,
qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not
used in many files. Move them out of osdep.h to a new
qemu/cacheinfo.h, and document them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org

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Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-pull-request' into staging

This fixes a Coverity report and improves the fid reclaim logic.

# gpg: Signature made Mon

Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-pull-request' into staging

This fixes a Coverity report and improves the fid reclaim logic.

# gpg: Signature made Mon 25 Jan 2021 09:37:28 GMT
# gpg: using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full]
# gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full]
# gpg: aka "[jpeg image of size 3330]" [full]
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6

* remotes/gkurz-gitlab/tags/9p-next-pull-request:
9pfs: Convert reclaim list to QSLIST
9pfs: Improve unreclaim loop
9pfs: Convert V9fsFidState::fid_list to QSIMPLEQ
9pfs: Convert V9fsFidState::clunked to bool
9pfs/proxy: Check return value of proxy_marshal()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210124' into staging

SD/MMC patches

- Various improvements for SD cards in SPI mode (Bin Meng)

# gpg: Signa

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210124' into staging

SD/MMC patches

- Various improvements for SD cards in SPI mode (Bin Meng)

# gpg: Signature made Sun 24 Jan 2021 19:16:55 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/sdmmc-20210124:
hw/sd: sd.h: Cosmetic change of using spaces
hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
hw/sd: ssi-sd: Add a state representing Nac
hw/sd: ssi-sd: Suffix a data block with CRC16
util: Add CRC16 (CCITT) calculation routines
hw/sd: sd: Drop sd_crc16()
hw/sd: sd: Support CMD59 for SPI mode
hw/sd: ssi-sd: Fix incorrect card response sequence

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210124' into staging

Fix tcg constant temp overflow.
Fix running during atomic single-step.
Partial support for apple

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210124' into staging

Fix tcg constant temp overflow.
Fix running during atomic single-step.
Partial support for apple silicon.
Cleanups for accel/tcg.

# gpg: Signature made Sun 24 Jan 2021 18:08:57 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210124:
tcg: Restart code generation when we run out of temps
tcg: Toggle page execution for Apple Silicon
accel/tcg: Restrict cpu_io_recompile() from other accelerators
accel/tcg: Declare missing cpu_loop_exit*() stubs
accel/tcg: Restrict tb_gen_code() from other accelerators
accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
accel/tcg: Make cpu_gen_init() static
tcg: Optimize inline dup_const for MO_64
qemu/compiler: Split out qemu_build_not_reached_always
tcg: update the cpu running flag in cpu_exec_step_atomic

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* Make MinGW respect --bindir (Joshua)
* Switch MinGW to a "deep" installation (Joshua + NSIS fixes b

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* Make MinGW respect --bindir (Joshua)
* Switch MinGW to a "deep" installation (Joshua + NSIS fixes by myself)
* Fix compilation errors/warnings (Qixin, Philippe)
* QemuOpts cleanups (myself)
* Consistency improvements for -action (myself)
* remove deprecated "change vnc TARGET" functionality (myself)
* meson cleanups (Marc-André, Philippe, myself)
* IDE out-of-bounds access (Prasad)
* LA57 fix for -cpu max (Weijiang)

# gpg: Signature made Sat 23 Jan 2021 20:55:59 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (30 commits)
qemu-option: warn for short-form boolean options
qemu-option: move help handling to get_opt_name_value
qemu-option: clean up id vs. list->merge_lists
vnc: support "-vnc help"
qmp: remove deprecated "change" command
hmp: remove "change vnc TARGET" command
acceptance: switch to QMP change-vnc-password command
meson.build: Detect bzip2 program
meson.build: Declare global edk2_targets / install_edk2_blobs variables
meson: Add a section header for library dependencies
meson: Display crypto-related information altogether
meson: Display block layer information altogether
meson: Display accelerators and selected targets altogether
meson: Summarize compilation-related information altogether
meson: Summarize overall features altogether
meson: Display host binaries information altogether
meson: Summarize information related to directories first
meson: convert wixl detection to Meson
nsis: adjust for new MinGW paths
meson: Declare have_virtfs_proxy_helper in main meson.build
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

util/cacheflush: Fix error generated by clang

When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
error:

../util/cacheflush.c:38:44: error: value size do

util/cacheflush: Fix error generated by clang

When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
error:

../util/cacheflush.c:38:44: error: value size does not match register size
specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
^
../util/cacheflush.c:38:24: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
^~
%w0

Modify the type of save_ctr_el0 to uint64_t to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
Message-Id: <20210115075656.717957-1-ganqixin@huawei.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

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util: Specialize flush_idcache_range for aarch64

For darwin, the CTR_EL0 register is not accessible, but there
are system routines that we can use.

For other hosts, copy the sin

util: Specialize flush_idcache_range for aarch64

For darwin, the CTR_EL0 register is not accessible, but there
are system routines that we can use.

For other hosts, copy the single pointer implementation from
libgcc and modify it to support the double pointer interface
we require. This halves the number of cache operations required
when split-rwx is enabled.

Reviewed-by: Joelle van Dyne <j@getutm.app>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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util: Enhance flush_icache_range with separate data pointer

We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data poin

util: Enhance flush_icache_range with separate data pointer

We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.

For now, the two passed pointers are identical, so there is no
effective change in behaviour.

Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

From Alex's pull request:
* improve cross-build KVM coverage
* new --without-default-features con

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

From Alex's pull request:
* improve cross-build KVM coverage
* new --without-default-features configure flag
* add __repr__ for ConsoleSocket for debugging
* build tcg tests with -Werror
* test 32 bit builds with fedora
* remove last traces of debian9
* hotfix for centos8 powertools repo

* Move lots of feature detection code to meson (Alex, myself)
* CFI and LTO support (Daniele)
* test-char dangling pointer (Eduardo)
* Build system and win32 fixes (Marc-André)
* Initialization fixes (myself)
* TCG include cleanup (Richard, myself)
* x86 'int N' fix (Peter)

# gpg: Signature made Wed 06 Jan 2021 09:21:25 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (52 commits)
win32: drop fd registration to the main-loop on setting non-block
configure: move tests/qemu-iotests/common.env generation to meson
meson.build: convert --with-default-devices to meson
libattr: convert to meson
cap_ng: convert to meson
virtfs: convert to meson
seccomp: convert to meson
zstd: convert to meson
lzfse: convert to meson
snappy: convert to meson
lzo: convert to meson
rbd: convert to meson
libnfs: convert to meson
libiscsi: convert to meson
bzip2: convert to meson
glusterfs: convert to meson
curl: convert to meson
curl: remove compatibility code, require 7.29.0
brlapi: convert to meson
configure: remove CONFIG_FILEVERSION and CONFIG_PRODUCTVERSION
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
# trace/meson.build

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util: Extract flush_icache_range to cacheflush.c

This has been a tcg-specific function, but is also in use
by hardware accelerators via physmem.c. This can cause
link errors when tc

util: Extract flush_icache_range to cacheflush.c

This has been a tcg-specific function, but is also in use
by hardware accelerators via physmem.c. This can cause
link errors when tcg is disabled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...