1 // SPDX-License-Identifier: GPL-2.0+
40 		gd->arch.l2_line_size = mips_cm_l2_line_size();  in probe_l2()
46 		gd->arch.l2_line_size = sl ? (2 << sl) : 0;  in probe_l2()
61 	gd->arch.l1i_line_size = il ? (2 << il) : 0;  in mips_cache_probe()
62 	gd->arch.l1d_line_size = dl ? (2 << dl) : 0;  in mips_cache_probe()
70 	return gd->arch.l1i_line_size;  in icache_line_size()
79 	return gd->arch.l1d_line_size;  in dcache_line_size()
88 	return gd->arch.l2_line_size;  in scache_line_size()
95 	const void *addr = (const void *)(start & ~(lsize - 1));	\
96 	const void *aend = (const void *)((end - 1) & ~(lsize - 1));	\
109 void flush_cache(ulong start_addr, ulong size)  in flush_cache()  argument
115 	/* aend will be miscalculated when size is zero, so we return here */  in flush_cache()
116 	if (size == 0)  in flush_cache()
120 		/* flush I-cache & D-cache simultaneously */  in flush_cache()
121 		cache_loop(start_addr, start_addr + size, ilsize,  in flush_cache()
126 	/* flush D-cache */  in flush_cache()
127 	cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);  in flush_cache()
129 	/* flush L2 cache */  in flush_cache()
130 	cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);  in flush_cache()
132 	/* flush I-cache */  in flush_cache()
133 	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);  in flush_cache()
136 	/* ensure cache ops complete before any further memory accesses */  in flush_cache()
139 	/* ensure the pipeline doesn't contain now-invalid instructions */  in flush_cache()
148 	/* aend will be miscalculated when size is zero, so we return here */  in flush_dcache_range()
154 	/* flush L2 cache */  in flush_dcache_range()
157 	/* ensure cache ops complete before any further memory accesses */  in flush_dcache_range()
166 	/* aend will be miscalculated when size is zero, so we return here */  in invalidate_dcache_range()
170 	/* invalidate L2 cache */  in invalidate_dcache_range()
175 	/* ensure cache ops complete before any further memory accesses */  in invalidate_dcache_range()
195 	/* ensure the pipeline doesn't contain now-invalid instructions */  in dcache_disable()