Lines Matching +full:cache +full:- +full:size
4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
27 #include "exec/page-protection.h"
29 #include "accel/tcg/cpu-ldst.h"
32 #include "user/page-protection.h"
70 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
77 /* Calculates TSB pointer value for fault page size
79 * UA2005 holds the page size configuration in mmu_ctx registers */
87 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
88 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
93 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
96 tsb_register = mmu->tsb; in ultrasparc_tsb_pointer()
105 uint64_t va = mmu->tag_access >> (3 * page_size + 9); in ultrasparc_tsb_pointer()
131 target_ulong mask, size, va, offset; in replace_tlb_entry() local
134 if (TTE_IS_VALID(tlb->tte)) { in replace_tlb_entry()
137 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); in replace_tlb_entry()
138 mask = 1ULL + ~size; in replace_tlb_entry()
140 va = tlb->tag & mask; in replace_tlb_entry()
142 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { in replace_tlb_entry()
147 tlb->tag = tlb_tag; in replace_tlb_entry()
148 tlb->tte = tlb_tte; in replace_tlb_entry()
163 context = env1->dmmu.mmu_primary_context; in demap_tlb()
166 context = env1->dmmu.mmu_secondary_context; in demap_tlb()
180 /* will remove non-global entries matching context value */ in demap_tlb()
248 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); in replace_tlb_1bit_lru() local
249 if (ranges_overlap(new_vaddr, new_size, vaddr, size)) { in replace_tlb_1bit_lru()
250 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, in replace_tlb_1bit_lru()
314 - note this list is defined by cpu implementation in is_translating_asi()
381 env->mxccdata[0], env->mxccdata[1], in dump_mxcc()
382 env->mxccdata[2], env->mxccdata[3]); in dump_mxcc()
387 env->mxccregs[0], env->mxccregs[1], in dump_mxcc()
388 env->mxccregs[2], env->mxccregs[3], in dump_mxcc()
389 env->mxccregs[4], env->mxccregs[5], in dump_mxcc()
390 env->mxccregs[6], env->mxccregs[7]); in dump_mxcc()
396 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, in dump_asi() argument
399 switch (size) { in dump_asi()
424 unsigned size, uintptr_t retaddr) in sparc_raise_mmu_fault() argument
433 is_exec ? "exec" : is_write ? "write" : "read", size, in sparc_raise_mmu_fault()
434 size == 1 ? "" : "s", addr, is_asi, env->pc); in sparc_raise_mmu_fault()
438 is_exec ? "exec" : is_write ? "write" : "read", size, in sparc_raise_mmu_fault()
439 size == 1 ? "" : "s", addr, env->pc); in sparc_raise_mmu_fault()
443 fault_type = (env->mmuregs[3] & 0x1c) >> 2; in sparc_raise_mmu_fault()
445 env->mmuregs[3] = 0; /* Fault status register */ in sparc_raise_mmu_fault()
447 env->mmuregs[3] |= 1 << 16; in sparc_raise_mmu_fault()
449 if (env->psrs) { in sparc_raise_mmu_fault()
450 env->mmuregs[3] |= 1 << 5; in sparc_raise_mmu_fault()
453 env->mmuregs[3] |= 1 << 6; in sparc_raise_mmu_fault()
456 env->mmuregs[3] |= 1 << 7; in sparc_raise_mmu_fault()
458 env->mmuregs[3] |= (5 << 2) | 2; in sparc_raise_mmu_fault()
461 env->mmuregs[4] = addr; /* Fault address register */ in sparc_raise_mmu_fault()
465 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { in sparc_raise_mmu_fault()
466 env->mmuregs[3] |= 1; in sparc_raise_mmu_fault()
469 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { in sparc_raise_mmu_fault()
475 * flush neverland mappings created during no-fault mode, in sparc_raise_mmu_fault()
478 if (env->mmuregs[0] & MMU_NF) { in sparc_raise_mmu_fault()
485 unsigned size, uintptr_t retaddr) in sparc_raise_mmu_fault() argument
491 "\n", addr, env->pc); in sparc_raise_mmu_fault()
495 if (env->lsu & (IMMU_E)) { in sparc_raise_mmu_fault()
497 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
501 if (env->lsu & (DMMU_E)) { in sparc_raise_mmu_fault()
503 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
515 /* Leon3 cache control */
518 uint64_t val, int size) in leon3_cache_control_st() argument
520 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", in leon3_cache_control_st()
521 addr, val, size); in leon3_cache_control_st()
523 if (size != 4) { in leon3_cache_control_st()
529 case 0x00: /* Cache control */ in leon3_cache_control_st()
538 env->cache_control = val; in leon3_cache_control_st()
540 case 0x04: /* Instruction cache configuration */ in leon3_cache_control_st()
541 case 0x08: /* Data cache configuration */ in leon3_cache_control_st()
551 int size) in leon3_cache_control_ld() argument
555 if (size != 4) { in leon3_cache_control_ld()
561 case 0x00: /* Cache control */ in leon3_cache_control_ld()
562 ret = env->cache_control; in leon3_cache_control_ld()
568 case 0x04: /* Instruction cache configuration */ in leon3_cache_control_ld()
571 case 0x08: /* Data cache configuration */ in leon3_cache_control_ld()
578 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", in leon3_cache_control_ld()
579 addr, ret, size); in leon3_cache_control_ld()
586 int size = 1 << (memop & MO_SIZE); in helper_ld_asi() local
594 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
597 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ in helper_ld_asi()
599 case 0x00: /* Leon3 Cache Control */ in helper_ld_asi()
600 case 0x08: /* Leon3 Instruction Cache config */ in helper_ld_asi()
601 case 0x0C: /* Leon3 Date Cache config */ in helper_ld_asi()
602 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_ld_asi()
603 ret = leon3_cache_control_ld(env, addr, size); in helper_ld_asi()
606 " address, size: %d\n", addr, size); in helper_ld_asi()
610 if (size == 8) { in helper_ld_asi()
611 ret = env->mxccregs[3]; in helper_ld_asi()
614 "%08x: unimplemented access size: %d\n", addr, in helper_ld_asi()
615 size); in helper_ld_asi()
619 if (size == 4) { in helper_ld_asi()
620 ret = env->mxccregs[3]; in helper_ld_asi()
623 "%08x: unimplemented access size: %d\n", addr, in helper_ld_asi()
624 size); in helper_ld_asi()
628 if (size == 8) { in helper_ld_asi()
629 ret = env->mxccregs[5]; in helper_ld_asi()
633 "%08x: unimplemented access size: %d\n", addr, in helper_ld_asi()
634 size); in helper_ld_asi()
638 if (size == 8) { in helper_ld_asi()
639 ret = env->mxccregs[7]; in helper_ld_asi()
642 "%08x: unimplemented access size: %d\n", addr, in helper_ld_asi()
643 size); in helper_ld_asi()
648 "%08x: unimplemented address, size: %d\n", addr, in helper_ld_asi()
649 size); in helper_ld_asi()
652 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " in helper_ld_asi()
653 "addr = %08x -> ret = %" PRIx64 "," in helper_ld_asi()
654 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); in helper_ld_asi()
670 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", in helper_ld_asi()
679 ret = env->mmuregs[reg]; in helper_ld_asi()
681 env->mmuregs[3] = 0; in helper_ld_asi()
683 ret = env->mmuregs[3]; in helper_ld_asi()
685 ret = env->mmuregs[4]; in helper_ld_asi()
694 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ in helper_ld_asi()
695 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ in helper_ld_asi()
696 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ in helper_ld_asi()
697 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ in helper_ld_asi()
704 switch (size) { in helper_ld_asi()
706 ret = address_space_ldub(cs->as, access_addr, in helper_ld_asi()
710 ret = address_space_lduw(cs->as, access_addr, in helper_ld_asi()
715 ret = address_space_ldl(cs->as, access_addr, in helper_ld_asi()
719 ret = address_space_ldq(cs->as, access_addr, in helper_ld_asi()
726 size, GETPC()); in helper_ld_asi()
730 case 0x30: /* Turbosparc secondary cache diagnostic */ in helper_ld_asi()
733 case 0x39: /* data cache diagnostic register */ in helper_ld_asi()
742 ret = env->mmubpregs[reg]; in helper_ld_asi()
745 ret = env->mmubpregs[reg]; in helper_ld_asi()
748 ret = env->mmubpregs[reg]; in helper_ld_asi()
751 ret = env->mmubpregs[reg]; in helper_ld_asi()
752 env->mmubpregs[reg] = 0ULL; in helper_ld_asi()
760 ret = env->mmubpctrv; in helper_ld_asi()
763 ret = env->mmubpctrc; in helper_ld_asi()
766 ret = env->mmubpctrs; in helper_ld_asi()
769 ret = env->mmubpaction; in helper_ld_asi()
772 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); in helper_ld_asi()
787 switch (size) { in helper_ld_asi()
802 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
810 int size = 1 << (memop & MO_SIZE); in helper_st_asi() local
813 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
816 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ in helper_st_asi()
818 case 0x00: /* Leon3 Cache Control */ in helper_st_asi()
819 case 0x08: /* Leon3 Instruction Cache config */ in helper_st_asi()
820 case 0x0C: /* Leon3 Date Cache config */ in helper_st_asi()
821 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_st_asi()
822 leon3_cache_control_st(env, addr, val, size); in helper_st_asi()
825 " address, size: %d\n", addr, size); in helper_st_asi()
830 if (size == 8) { in helper_st_asi()
831 env->mxccdata[0] = val; in helper_st_asi()
834 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
835 size); in helper_st_asi()
839 if (size == 8) { in helper_st_asi()
840 env->mxccdata[1] = val; in helper_st_asi()
843 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
844 size); in helper_st_asi()
848 if (size == 8) { in helper_st_asi()
849 env->mxccdata[2] = val; in helper_st_asi()
852 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
853 size); in helper_st_asi()
857 if (size == 8) { in helper_st_asi()
858 env->mxccdata[3] = val; in helper_st_asi()
861 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
862 size); in helper_st_asi()
869 if (size == 8) { in helper_st_asi()
870 env->mxccregs[0] = val; in helper_st_asi()
873 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
874 size); in helper_st_asi()
879 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; in helper_st_asi()
881 env->mxccdata[i] = address_space_ldq(cs->as, in helper_st_asi()
888 false, size, GETPC()); in helper_st_asi()
897 if (size == 8) { in helper_st_asi()
898 env->mxccregs[1] = val; in helper_st_asi()
901 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
902 size); in helper_st_asi()
907 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; in helper_st_asi()
909 address_space_stq(cs->as, access_addr, env->mxccdata[i], in helper_st_asi()
915 false, size, GETPC()); in helper_st_asi()
921 if (size == 8) { in helper_st_asi()
922 env->mxccregs[3] = val; in helper_st_asi()
925 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
926 size); in helper_st_asi()
930 if (size == 4) { in helper_st_asi()
931 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) in helper_st_asi()
935 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
936 size); in helper_st_asi()
941 if (size == 8) { in helper_st_asi()
942 env->mxccregs[6] &= ~val; in helper_st_asi()
945 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
946 size); in helper_st_asi()
950 if (size == 8) { in helper_st_asi()
951 env->mxccregs[7] = val; in helper_st_asi()
954 "%08x: unimplemented access size: %d\n", addr, in helper_st_asi()
955 size); in helper_st_asi()
960 "%08x: unimplemented address, size: %d\n", addr, in helper_st_asi()
961 size); in helper_st_asi()
964 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", in helper_st_asi()
965 asi, size, addr, val); in helper_st_asi()
1001 oldreg = env->mmuregs[reg]; in helper_st_asi()
1004 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | in helper_st_asi()
1006 /* Mappings generated during no-fault mode in helper_st_asi()
1008 if ((oldreg ^ env->mmuregs[reg]) in helper_st_asi()
1009 & (MMU_NF | env->def.mmu_bm)) { in helper_st_asi()
1014 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; in helper_st_asi()
1017 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; in helper_st_asi()
1018 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1028 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; in helper_st_asi()
1032 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; in helper_st_asi()
1035 env->mmuregs[4] = val; in helper_st_asi()
1038 env->mmuregs[reg] = val; in helper_st_asi()
1041 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1042 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", in helper_st_asi()
1043 reg, oldreg, env->mmuregs[reg]); in helper_st_asi()
1054 case ASI_M_TXTC_TAG: /* I-cache tag */ in helper_st_asi()
1055 case ASI_M_TXTC_DATA: /* I-cache data */ in helper_st_asi()
1056 case ASI_M_DATAC_TAG: /* D-cache tag */ in helper_st_asi()
1057 case ASI_M_DATAC_DATA: /* D-cache data */ in helper_st_asi()
1058 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ in helper_st_asi()
1059 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ in helper_st_asi()
1060 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ in helper_st_asi()
1061 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ in helper_st_asi()
1062 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ in helper_st_asi()
1069 switch (size) { in helper_st_asi()
1071 address_space_stb(cs->as, access_addr, val, in helper_st_asi()
1075 address_space_stw(cs->as, access_addr, val, in helper_st_asi()
1080 address_space_stl(cs->as, access_addr, val, in helper_st_asi()
1084 address_space_stq(cs->as, access_addr, val, in helper_st_asi()
1090 size, GETPC()); in helper_st_asi()
1094 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ in helper_st_asi()
1095 case 0x31: /* store buffer data, Ross RT620 I-cache flush or in helper_st_asi()
1099 case 0x36: /* I-cache flash clear */ in helper_st_asi()
1100 case 0x37: /* D-cache flash clear */ in helper_st_asi()
1108 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1111 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1114 env->mmubpregs[reg] = (val & 0x7fULL); in helper_st_asi()
1117 env->mmubpregs[reg] = (val & 0xfULL); in helper_st_asi()
1121 env->mmuregs[reg]); in helper_st_asi()
1125 env->mmubpctrv = val & 0xffffffff; in helper_st_asi()
1128 env->mmubpctrc = val & 0x3; in helper_st_asi()
1131 env->mmubpctrs = val & 0x3; in helper_st_asi()
1134 env->mmubpaction = val & 0x1fff; in helper_st_asi()
1139 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); in helper_st_asi()
1153 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1207 int size = 1 << (memop & MO_SIZE); in helper_ld_asi() local
1214 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1218 case ASI_PNF: /* Primary no-fault */ in helper_ld_asi()
1219 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1220 case ASI_SNF: /* Secondary no-fault */ in helper_ld_asi()
1221 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1222 if (!page_check_range(addr, size, PAGE_READ)) { in helper_ld_asi()
1226 switch (size) { in helper_ld_asi()
1258 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1259 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1260 switch (size) { in helper_ld_asi()
1275 switch (size) { in helper_ld_asi()
1288 dump_asi("read", addr, asi, size, ret); in helper_ld_asi()
1296 int size = 1 << (memop & MO_SIZE); in helper_st_asi() local
1298 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1303 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1313 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1314 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1315 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1316 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()
1327 int size = 1 << (memop & MO_SIZE); in helper_ld_asi() local
1338 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1348 int idx = (env->pstate & PS_PRIV in helper_ld_asi()
1352 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { in helper_ld_asi()
1354 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1357 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); in helper_ld_asi()
1360 switch (size) { in helper_ld_asi()
1388 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_ld_asi()
1390 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_ld_asi()
1419 ret = env->lsu; in helper_ld_asi()
1421 case ASI_IMMU: /* I-MMU regs */ in helper_ld_asi()
1426 /* 0x00 I-TSB Tag Target register */ in helper_ld_asi()
1427 ret = ultrasparc_tag_target(env->immu.tag_access); in helper_ld_asi()
1430 ret = env->immu.sfsr; in helper_ld_asi()
1433 ret = env->immu.tsb; in helper_ld_asi()
1436 /* 0x30 I-TSB Tag Access register */ in helper_ld_asi()
1437 ret = env->immu.tag_access; in helper_ld_asi()
1440 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); in helper_ld_asi()
1445 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ in helper_ld_asi()
1447 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1448 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1449 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); in helper_ld_asi()
1452 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ in helper_ld_asi()
1454 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1455 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1456 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); in helper_ld_asi()
1459 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_ld_asi()
1463 ret = env->itlb[reg].tte; in helper_ld_asi()
1466 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ in helper_ld_asi()
1470 ret = env->itlb[reg].tag; in helper_ld_asi()
1473 case ASI_DMMU: /* D-MMU regs */ in helper_ld_asi()
1478 /* 0x00 D-TSB Tag Target register */ in helper_ld_asi()
1479 ret = ultrasparc_tag_target(env->dmmu.tag_access); in helper_ld_asi()
1482 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1485 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1488 ret = env->dmmu.sfsr; in helper_ld_asi()
1491 ret = env->dmmu.sfar; in helper_ld_asi()
1494 ret = env->dmmu.tsb; in helper_ld_asi()
1496 case 6: /* 0x30 D-TSB Tag Access register */ in helper_ld_asi()
1497 ret = env->dmmu.tag_access; in helper_ld_asi()
1500 ret = env->dmmu.virtual_watchpoint; in helper_ld_asi()
1503 ret = env->dmmu.physical_watchpoint; in helper_ld_asi()
1506 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); in helper_ld_asi()
1511 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ in helper_ld_asi()
1513 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1514 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1515 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); in helper_ld_asi()
1518 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ in helper_ld_asi()
1520 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1521 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1522 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); in helper_ld_asi()
1525 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_ld_asi()
1529 ret = env->dtlb[reg].tte; in helper_ld_asi()
1532 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ in helper_ld_asi()
1536 ret = env->dtlb[reg].tag; in helper_ld_asi()
1542 ret = env->ivec_status; in helper_ld_asi()
1548 ret = env->ivec_data[reg]; in helper_ld_asi()
1555 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); in helper_ld_asi()
1561 ret = env->scratch[i]; in helper_ld_asi()
1567 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1570 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1573 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_ld_asi()
1576 case ASI_DCACHE_DATA: /* D-cache data */ in helper_ld_asi()
1577 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_ld_asi()
1578 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_ld_asi()
1579 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_ld_asi()
1580 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_ld_asi()
1581 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_ld_asi()
1582 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_ld_asi()
1583 case ASI_IC_TAG: /* I-cache tag access */ in helper_ld_asi()
1584 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_ld_asi()
1585 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_ld_asi()
1586 case ASI_EC_W: /* E-cache tag */ in helper_ld_asi()
1587 case ASI_EC_R: /* E-cache tag */ in helper_ld_asi()
1589 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ in helper_ld_asi()
1590 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ in helper_ld_asi()
1591 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ in helper_ld_asi()
1592 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ in helper_ld_asi()
1593 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ in helper_ld_asi()
1596 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); in helper_ld_asi()
1603 switch (size) { in helper_ld_asi()
1618 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1626 int size = 1 << (memop & MO_SIZE); in helper_st_asi() local
1630 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1636 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1649 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_st_asi()
1651 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_st_asi()
1671 /* these ASIs have different functions on UltraSPARC-IIIi in helper_st_asi()
1686 env->dmmu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1698 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1715 env->immu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1727 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1736 env->lsu = val & (DMMU_E | IMMU_E); in helper_st_asi()
1738 case ASI_IMMU: /* I-MMU regs */ in helper_st_asi()
1743 oldreg = env->immu.mmuregs[reg]; in helper_st_asi()
1747 case 1: /* Not in I-MMU */ in helper_st_asi()
1754 env->immu.sfsr = val; in helper_st_asi()
1759 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1760 PRIx64 "\n", env->immu.tsb, val); in helper_st_asi()
1761 env->immu.tsb = val; in helper_st_asi()
1764 env->immu.tag_access = val; in helper_st_asi()
1770 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_st_asi()
1774 if (oldreg != env->immu.mmuregs[reg]) { in helper_st_asi()
1775 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1776 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); in helper_st_asi()
1783 case ASI_ITLB_DATA_IN: /* I-MMU data in */ in helper_st_asi()
1786 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, in helper_st_asi()
1790 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_st_asi()
1798 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, in helper_st_asi()
1807 case ASI_IMMU_DEMAP: /* I-MMU demap */ in helper_st_asi()
1808 demap_tlb(env->itlb, addr, "immu", env); in helper_st_asi()
1810 case ASI_DMMU: /* D-MMU regs */ in helper_st_asi()
1815 oldreg = env->dmmu.mmuregs[reg]; in helper_st_asi()
1823 env->dmmu.sfar = 0; in helper_st_asi()
1825 env->dmmu.sfsr = val; in helper_st_asi()
1828 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1834 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1840 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1841 PRIx64 "\n", env->dmmu.tsb, val); in helper_st_asi()
1842 env->dmmu.tsb = val; in helper_st_asi()
1845 env->dmmu.tag_access = val; in helper_st_asi()
1848 env->dmmu.virtual_watchpoint = val; in helper_st_asi()
1851 env->dmmu.physical_watchpoint = val; in helper_st_asi()
1854 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_st_asi()
1858 if (oldreg != env->dmmu.mmuregs[reg]) { in helper_st_asi()
1859 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1860 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); in helper_st_asi()
1867 case ASI_DTLB_DATA_IN: /* D-MMU data in */ in helper_st_asi()
1870 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, in helper_st_asi()
1874 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_st_asi()
1880 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, in helper_st_asi()
1889 case ASI_DMMU_DEMAP: /* D-MMU demap */ in helper_st_asi()
1890 demap_tlb(env->dtlb, addr, "dmmu", env); in helper_st_asi()
1893 env->ivec_status = val & 0x20; in helper_st_asi()
1898 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_st_asi()
1904 env->scratch[i] = val; in helper_st_asi()
1911 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1912 env->immu.mmu_primary_context = val; in helper_st_asi()
1917 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1918 env->immu.mmu_secondary_context = val; in helper_st_asi()
1924 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_st_asi()
1929 case ASI_DCACHE_DATA: /* D-cache data */ in helper_st_asi()
1930 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_st_asi()
1931 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_st_asi()
1932 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_st_asi()
1933 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_st_asi()
1934 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_st_asi()
1935 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_st_asi()
1936 case ASI_IC_TAG: /* I-cache tag access */ in helper_st_asi()
1937 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_st_asi()
1938 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_st_asi()
1939 case ASI_EC_W: /* E-cache tag */ in helper_st_asi()
1940 case ASI_EC_R: /* E-cache tag */ in helper_st_asi()
1942 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ in helper_st_asi()
1943 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ in helper_st_asi()
1944 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ in helper_st_asi()
1945 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ in helper_st_asi()
1946 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ in helper_st_asi()
1947 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ in helper_st_asi()
1948 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ in helper_st_asi()
1951 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1952 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1953 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1954 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()
1956 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); in helper_st_asi()
1968 vaddr addr, unsigned size, in sparc_cpu_do_transaction_failed() argument
1978 is_asi, size, retaddr); in sparc_cpu_do_transaction_failed()