5  * See the COPYING file in the top-level directory.
12 #include "qemu/host-utils.h"
22  * Operating system specific cache detection mechanisms.
30     DWORD size = 0;  in sys_cache_info()  local
35      * Check for the required buffer size first.  Note that if the zero  in sys_cache_info()
36      * size we use for the probe results in success, then there is no  in sys_cache_info()
39     success = GetLogicalProcessorInformation(0, &size);  in sys_cache_info()
44     n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);  in sys_cache_info()
45     size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);  in sys_cache_info()
47     if (!GetLogicalProcessorInformation(buf, &size)) {  in sys_cache_info()
53             && buf[i].Cache.Level == 1) {  in sys_cache_info()
54             switch (buf[i].Cache.Type) {  in sys_cache_info()
56                 *isize = *dsize = buf[i].Cache.LineSize;  in sys_cache_info()
59                 *isize = buf[i].Cache.LineSize;  in sys_cache_info()
62                 *dsize = buf[i].Cache.LineSize;  in sys_cache_info()
77     /* There's only a single sysctl for both I/D cache line sizes.  */  in sys_cache_info()
78     long size;  in sys_cache_info()  local
79     size_t len = sizeof(size);  in sys_cache_info()
80     if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {  in sys_cache_info()
81         *isize = *dsize = size;  in sys_cache_info()
88     /* There's only a single sysctl for both I/D cache line sizes.  */  in sys_cache_info()
89     int size;  in sys_cache_info()  local
90     size_t len = sizeof(size);  in sys_cache_info()
91     if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {  in sys_cache_info()
92         *isize = *dsize = size;  in sys_cache_info()
117  * Architecture (+ OS) specific cache detection mechanisms.
136      * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,  in arch_cache_info()
139      * entire hierarchy, and is used by userspace cache flushing.  in arch_cache_info()
192          * For PPC, we're going to use the cache sizes computed for  in fallback_cache_info()
212     assert((isize & (isize - 1)) == 0);  in init_cache_info()
213     assert((dsize & (dsize - 1)) == 0);  in init_cache_info()
225  * Architecture (+ OS) specific cache flushing mechanisms.
262  * to fit this three-operand interface.
274      * If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification  in flush_idcache_range()
279          * Loop over the address range, clearing one cache line at once.  in flush_idcache_range()
280          * Data cache must be flushed to unification first to make sure  in flush_idcache_range()
281          * the instruction cache fetches the updated data.  in flush_idcache_range()
283         for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) {  in flush_idcache_range()
292      * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point  in flush_idcache_range()
296         for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) {  in flush_idcache_range()
332      *   POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)   in flush_idcache_range()
346     b = rw & ~(dsize - 1);  in flush_idcache_range()
347     e = (rw + len + dsize - 1) & ~(dsize - 1);  in flush_idcache_range()
353     b = rx & ~(isize - 1);  in flush_idcache_range()
354     e = (rx + len + isize - 1) & ~(isize - 1);  in flush_idcache_range()
367     uintptr_t p, end = (rx + len + 7) & -8;  in flush_idcache_range()
368     for (p = rx & -8; p < end; p += 8) {  in flush_idcache_range()