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592cd5de |
| 02-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Si
Merge branch 'master' of git://git.denx.de/u-boot-spi This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
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d29a5831 |
| 29-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'mpc85xx-for-v2018.11-rc1' of git://git.denx.de/u-boot-mpc85xx Use device tree for mpc85xx with binman. Enabled for T2080QDS.
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27f622d5 |
| 29-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A.
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
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0ae8dcfe |
| 26-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot Patch queue for efi - 2018-09-26 A lot of goodness in this release. We're *very* close to running the UEFI Shell and
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot Patch queue for efi - 2018-09-26 A lot of goodness in this release. We're *very* close to running the UEFI Shell and SCT natively. The only missing piece are HII protocols. - FAT write support (needed for SCT) - improved FAT directory support (needed for SCT) - RTC support with QEMU -M virt - Sandbox support (run UEFI binaries in Linux - yay) - Proper UTF-16 support - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell) - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell) - Fix window size determination - Fix Tegra by explicitly unmapping RAM - Clean up handle entanglement - Lots of generic code cleanup [trini: Fixup merge conflict in include/configs/qemu-arm.h] Signed-off-by: Tom Rini <trini@konsulko.com>
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2f85c2be |
| 07-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: cache: reimplement dcache_[status, enable, disable] Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when
MIPS: cache: reimplement dcache_[status, enable, disable] Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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e8f80a5a |
| 09-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-sunxi
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83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borro
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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b55c89ce |
| 19-Dec-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-spi
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76cc3728 |
| 19-Dec-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-sunxi
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b06c46de |
| 29-Nov-2017 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
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fcc8250c |
| 28-Nov-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-mips
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cc4f3643 |
| 21-Nov-2017 |
Paul Burton <paul.burton@mips.com> |
MIPS: Break out of cache loops for unimplemented caches If we run on a CPU which doesn't implement a particular cache then we would previously get stuck in an infinite loop, executing a
MIPS: Break out of cache loops for unimplemented caches If we run on a CPU which doesn't implement a particular cache then we would previously get stuck in an infinite loop, executing a cache op on the first "line" of the missing cache & then incrementing the address by 0. This was being avoided for the L2 caches, but not for the L1s. Fix this by generalising the check for a zero line size & avoiding the cache op loop when this is the case. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
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d8b32697 |
| 21-Nov-2017 |
Paul Burton <paul.burton@mips.com> |
MIPS: Clear instruction hazards in flush_cache() When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to
MIPS: Clear instruction hazards in flush_cache() When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
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219c2db3 |
| 21-Nov-2017 |
Paul Burton <paul.burton@mips.com> |
MIPS: Ensure cache ops complete in cache maintenance functions A typical use of cache maintenance functions is to force writeback of data which a device is about to read using DMA - for
MIPS: Ensure cache ops complete in cache maintenance functions A typical use of cache maintenance functions is to force writeback of data which a device is about to read using DMA - for example a descriptor or command structure. Such users of cache maintenance functions require that operations on the cache have completed before they proceed to instruct a device to read memory. This requires that we place a completion barrier (ie. sync instruction) between the cache ops and whatever write informs the device to perform DMA. Whilst strictly speaking this isn't all users of the cache maintenance functions & we could instead place the barriers in the drivers that require them, it would be much more invasive to do so than to just have the barrier be the default by placing it in the cache functions themselves. The cost is low enough that it shouldn't matter to us in any rare cases that we use the cache functions when not performing DMA. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
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22f3368e |
| 13-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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939a255a |
| 12-May-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Make CM GCR base configurable Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow defconfigs to set it. Provide the prompt in order to allow for that. S
MIPS: Make CM GCR base configurable Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow defconfigs to set it. Provide the prompt in order to allow for that. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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cbe7706a |
| 26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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201c9d88 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip
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19d051a2 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
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58c8c096 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
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423620b9 |
| 21-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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4baa0ab6 |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: L2 cache support This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or
MIPS: L2 cache support This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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8cb4817d |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Probe cache line sizes once during boot Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in
MIPS: Probe cache line sizes once during boot Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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2313d484 |
| 20-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-nand-flash
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6beacfcf |
| 18-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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