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/openbmc/linux/drivers/gpio/
H A Dgpio-omap.c78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
[all …]
H A Dgpio-rockchip.c76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
93 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
105 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
108 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
[all …]
H A Dgpio-brcmstb.c26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
[all …]
/openbmc/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
63 local BANK=$2
65 mkdir $CONFIGFS_DIR/$CHIP/$BANK
70 local BANK=$2
[all …]
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dsh_pfc.h356 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
357 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
358 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
360 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
361 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
362 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
363 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
364 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
365 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) argument
367 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
[all …]
/openbmc/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h441 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
442 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
443 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
445 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
446 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
447 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
448 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
450 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
451 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
452 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json210 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
219 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
228 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
237 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
529 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
533 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
537 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
541 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
546 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
550 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json177 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
186 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
195 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
204 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
496 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
500 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
504 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
508 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
513 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
517 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json203 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
212 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
221 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
230 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
522 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
526 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
530 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
534 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
539 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
543 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/openbmc/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
H A Dadf_gen4_hw_data.h28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
30 ADF_RING_BUNDLE_SIZE * (bank) + \
32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_RING_BUNDLE_SIZE * (bank) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
38 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
41 ADF_RING_BUNDLE_SIZE * (bank) + \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
46 u32 _bank = bank; \
[all …]
H A Dadf_transport_debug.c44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
60 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
59 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
63 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
65 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
[all …]
/openbmc/u-boot/cmd/
H A Dflash.c35 * the syntax is B:SF[-SL], where B is the bank number, SF is the first
37 * bank numbers start at 1 to be consistent with other specs, sector numbers
45 * or an invalid flash bank.
51 int bank, first, last; in abbrev_spec() local
58 bank = simple_strtoul (str, &ep, 10); in abbrev_spec()
60 bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || in abbrev_spec()
61 (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) in abbrev_spec()
94 ulong bank, sector_end_addr; in flash_sect_roundb() local
100 for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS && !found; ++bank) { in flash_sect_roundb()
101 info = &flash_info[bank]; in flash_sect_roundb()
[all …]
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_exti.c69 static unsigned valid_mask(unsigned bank) in valid_mask() argument
71 return MAKE_64BIT_MASK(0, irqs_per_bank[bank]); in valid_mask()
74 static unsigned configurable_mask(unsigned bank) in configurable_mask() argument
76 return valid_mask(bank) & ~exti_romask[bank]; in configurable_mask()
83 for (unsigned bank = 0; bank < EXTI_NUM_REGISTER; bank++) { in stm32l4x5_exti_reset_hold() local
84 s->imr[bank] = exti_romask[bank]; in stm32l4x5_exti_reset_hold()
85 s->emr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
86 s->rtsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
87 s->ftsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
88 s->swier[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c62 int bank; member
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
110 int bank = lanes[lane].bank; in serdes_lane_enabled() local
114 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
123 if (bank > 0) in serdes_lane_enabled()
124 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
181 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
224 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is in __serdes_reset_rx()
234 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is in __serdes_reset_rx()
271 * Enable a SERDES bank that was disabled via the RCW
[all …]
/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/openbmc/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
[all …]
/openbmc/linux/drivers/bus/
H A Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json221 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
230 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
239 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
248 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
543 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
550 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
558 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
566 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
574 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]
/openbmc/linux/arch/x86/kernel/cpu/mce/
H A Damd.c145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
149 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
152 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
223 * So to define a unique name for each bank, we use a temp c-string to append
252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
270 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
274 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
[all …]
/openbmc/u-boot/board/toradex/colibri_imx6/
H A Dpf0100_otp.inc72 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
73 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
74 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/openbmc/u-boot/board/toradex/apalis_imx6/
H A Dpf0100_otp.inc74 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dintel_ich6_gpio.c21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
57 static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset, in _ich6_gpio_set_value() argument
62 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
63 val = bank->lvl_write_cache; in _ich6_gpio_set_value()
65 val = inl(bank->lvl); in _ich6_gpio_set_value()
71 outl(val, bank->lvl); in _ich6_gpio_set_value()
72 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
73 bank->lvl_write_cache = val; in _ich6_gpio_set_value()
114 "bank-name", NULL); in gpio_ich6_ofdata_to_platdata()
[all …]
H A Ds5p_gpio.c35 /* Platform data for each bank */
37 struct s5p_gpio_bank *bank; member
41 /* Information about each bank at run-time */
43 struct s5p_gpio_bank *bank; member
59 struct s5p_gpio_bank *bank; in s5p_gpio_get_bank() local
60 bank = (struct s5p_gpio_bank *)data->reg_addr; in s5p_gpio_get_bank()
61 bank += (gpio - upto) / GPIO_PER_BANK; in s5p_gpio_get_bank()
62 debug("gpio=%d, bank=%p\n", gpio, bank); in s5p_gpio_get_bank()
63 return bank; in s5p_gpio_get_bank()
73 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) in s5p_gpio_cfg_pin() argument
[all …]

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