Lines Matching full:bank

72 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
73 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
74 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
88 // PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
90 // BANK 1
92 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
93 {pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
94 {pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
95 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
96 {pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
97 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
99 // BANK 2
101 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
102 {pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
103 {pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
104 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
105 {pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
106 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
108 // BANK 3
110 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
111 {pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
112 {pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
113 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
114 {pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
115 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
117 // BANK 4
119 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
120 {pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
121 {pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
122 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
123 {pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
124 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
126 // BANK 5
128 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
129 {pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
130 {pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
131 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
132 {pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
133 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
135 // BANK 6
137 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
138 {pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
139 {pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
140 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
141 {pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
142 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
144 // BANK 7
146 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
147 {pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
148 {pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
149 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
150 {pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
151 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
153 // BANK 8
155 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
156 {pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
157 {pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
158 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
159 {pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
160 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
162 // BANK 9
164 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
165 {pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
166 {pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
167 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
168 {pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
169 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
171 // BANK 10
173 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
174 {pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
175 {pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
176 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
177 {pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
178 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits