Lines Matching full:bank

74 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
90 // PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
92 // BANK 1
94 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
95 {pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
96 {pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
97 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
98 {pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
99 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
101 // BANK 2
103 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
104 {pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
105 {pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
106 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
107 {pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
108 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
110 // BANK 3
112 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
113 {pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
114 {pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
115 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
116 {pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
117 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
119 // BANK 4
121 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
122 {pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
123 {pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
124 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
125 {pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
126 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
128 // BANK 5
130 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
131 {pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
132 {pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
133 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
134 {pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
135 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
137 // BANK 6
139 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
140 {pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
141 {pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
142 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
143 {pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
144 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
146 // BANK 7
148 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
149 {pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
150 {pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
151 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
152 {pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
153 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
155 // BANK 8
157 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
158 {pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
159 {pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
160 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
161 {pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
162 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
164 // BANK 9
166 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
167 {pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
168 {pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
169 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
170 {pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
171 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
173 // BANK 10
175 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
176 {pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
177 {pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
178 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
179 {pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
180 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits