Lines Matching full:bank
26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
67 return bank->parent_priv; in brcmstb_gpio_gc_to_priv()
71 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in __brcmstb_gpio_get_active_irqs() argument
73 void __iomem *reg_base = bank->parent_priv->reg_base; in __brcmstb_gpio_get_active_irqs()
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & in __brcmstb_gpio_get_active_irqs()
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); in __brcmstb_gpio_get_active_irqs()
80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_get_active_irqs() argument
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
86 status = __brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_get_active_irqs()
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
93 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_hwirq_to_offset() argument
95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); in brcmstb_gpio_hwirq_to_offset()
98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, in brcmstb_gpio_set_imask() argument
101 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_set_imask()
102 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_set_imask()
103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); in brcmstb_gpio_set_imask()
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_mask() local
135 brcmstb_gpio_set_imask(bank, d->hwirq, false); in brcmstb_gpio_irq_mask()
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_unmask() local
143 brcmstb_gpio_set_imask(bank, d->hwirq, true); in brcmstb_gpio_irq_unmask()
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_ack() local
150 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_ack()
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_ack()
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); in brcmstb_gpio_irq_ack()
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_type() local
160 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_type()
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_type()
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
199 iedge_config = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
200 GIO_EC(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
202 GIO_EI(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
203 ilevel = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
204 GIO_LEVEL(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_wake() local
236 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_wake()
237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_wake()
244 bank->wake_active |= mask; in brcmstb_gpio_irq_set_wake()
246 bank->wake_active &= ~mask; in brcmstb_gpio_irq_set_wake()
262 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_irq_bank_handler() argument
264 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_bank_handler()
266 int hwbase = bank->gc.base - priv->gpio_base; in brcmstb_gpio_irq_bank_handler()
269 while ((status = brcmstb_gpio_get_active_irqs(bank))) { in brcmstb_gpio_irq_bank_handler()
273 if (offset >= bank->width) in brcmstb_gpio_irq_bank_handler()
275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", in brcmstb_gpio_irq_bank_handler()
276 bank->id, offset); in brcmstb_gpio_irq_bank_handler()
287 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_irq_handler() local
293 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_irq_handler()
294 brcmstb_gpio_irq_bank_handler(bank); in brcmstb_gpio_irq_handler()
301 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_hwirq_to_bank() local
305 list_for_each_entry_reverse(bank, &priv->bank_list, node) { in brcmstb_gpio_hwirq_to_bank()
306 i += bank->gc.ngpio; in brcmstb_gpio_hwirq_to_bank()
308 return bank; in brcmstb_gpio_hwirq_to_bank()
325 struct brcmstb_gpio_bank *bank = in brcmstb_gpio_irq_map() local
330 if (!bank) in brcmstb_gpio_irq_map()
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", in brcmstb_gpio_irq_map()
334 irq, (int)hwirq, bank->id); in brcmstb_gpio_irq_map()
335 ret = irq_set_chip_data(irq, &bank->gc); in brcmstb_gpio_irq_map()
363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); in brcmstb_gpio_sanity_check_banks()
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", in brcmstb_gpio_sanity_check_banks()
377 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_remove() local
396 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_remove()
397 gpiochip_remove(&bank->gc); in brcmstb_gpio_remove()
406 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_of_xlate() local
421 if (unlikely(offset >= bank->width)) { in brcmstb_gpio_of_xlate()
498 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_save() argument
500 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_save()
504 bank->saved_regs[i] = gc->read_reg(priv->reg_base + in brcmstb_gpio_bank_save()
505 GIO_BANK_OFF(bank->id, i)); in brcmstb_gpio_bank_save()
511 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_quiesce() local
519 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_quiesce()
520 gc = &bank->gc; in brcmstb_gpio_quiesce()
523 brcmstb_gpio_bank_save(priv, bank); in brcmstb_gpio_quiesce()
527 imask = bank->wake_active; in brcmstb_gpio_quiesce()
530 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), in brcmstb_gpio_quiesce()
543 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_restore() argument
545 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_restore()
549 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), in brcmstb_gpio_bank_restore()
550 bank->saved_regs[i]); in brcmstb_gpio_bank_restore()
562 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_resume() local
565 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_resume()
566 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_resume()
567 brcmstb_gpio_bank_restore(priv, bank); in brcmstb_gpio_resume()
643 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, in brcmstb_gpio_probe()
645 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_probe() local
649 * If bank_width is 0, then there is an empty bank in the in brcmstb_gpio_probe()
653 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", in brcmstb_gpio_probe()
660 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in brcmstb_gpio_probe()
661 if (!bank) { in brcmstb_gpio_probe()
666 bank->parent_priv = priv; in brcmstb_gpio_probe()
667 bank->id = num_banks; in brcmstb_gpio_probe()
669 dev_err(dev, "Invalid bank width %d\n", bank_width); in brcmstb_gpio_probe()
673 bank->width = bank_width; in brcmstb_gpio_probe()
680 gc = &bank->gc; in brcmstb_gpio_probe()
682 reg_base + GIO_DATA(bank->id), in brcmstb_gpio_probe()
684 reg_base + GIO_IODIR(bank->id), flags); in brcmstb_gpio_probe()
699 /* not all ngpio lines are valid, will use bank width later */ in brcmstb_gpio_probe()
701 gc->offset = bank->id * MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
709 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_probe()
710 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
712 err = gpiochip_add_data(gc, bank); in brcmstb_gpio_probe()
714 dev_err(dev, "Could not add gpiochip for bank %d\n", in brcmstb_gpio_probe()
715 bank->id); in brcmstb_gpio_probe()
720 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, in brcmstb_gpio_probe()
721 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()
723 /* Everything looks good, so add bank to list */ in brcmstb_gpio_probe()
724 list_add(&bank->node, &priv->bank_list); in brcmstb_gpio_probe()