Lines Matching full:bank
145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
149 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
152 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
223 * So to define a unique name for each bank, we use a temp c-string to append
252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
270 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
274 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
287 * bank. It also means that the OS will configure deferred in smca_configure()
296 * SMCA sets the Deferred Error Interrupt type per bank. in smca_configure()
309 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); in smca_configure()
314 smca_set_misc_banks_map(bank, cpu); in smca_configure()
316 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { in smca_configure()
317 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); in smca_configure()
328 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; in smca_configure()
329 this_cpu_ptr(smca_banks)[bank].id = low; in smca_configure()
330 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; in smca_configure()
344 static inline bool is_shared_bank(int bank) in is_shared_bank() argument
348 * a shared bank. in is_shared_bank()
353 /* Bank 4 is for northbridge reporting and is thus shared */ in is_shared_bank()
354 return (bank == 4); in is_shared_bank()
377 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) in lvt_interrupt_supported() argument
380 * bank 4 supports APIC LVT interrupts implicitly since forever. in lvt_interrupt_supported()
382 if (bank == 4) in lvt_interrupt_supported()
387 * bank can generate APIC LVT interrupts in lvt_interrupt_supported()
398 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, in lvt_off_valid()
399 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
413 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", in lvt_off_valid()
414 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
421 /* Reprogram MCx_MISC MSR behind this threshold bank. */
527 static u32 smca_get_block_address(unsigned int bank, unsigned int block, in smca_get_block_address() argument
531 return MSR_AMD64_SMCA_MCx_MISC(bank); in smca_get_block_address()
533 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) in smca_get_block_address()
536 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); in smca_get_block_address()
540 unsigned int bank, unsigned int block, in get_block_address() argument
545 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) in get_block_address()
549 return smca_get_block_address(bank, block, cpu); in get_block_address()
554 addr = mca_msr_reg(bank, MCA_MISC); in get_block_address()
568 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, in prepare_threshold_block() argument
577 per_cpu(bank_map, cpu) |= BIT_ULL(bank); in prepare_threshold_block()
581 b.bank = bank; in prepare_threshold_block()
584 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); in prepare_threshold_block()
616 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in amd_filter_mce()
627 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) in amd_filter_mce()
637 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
640 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) in disable_err_thresholding() argument
647 if (c->x86 == 0x15 && bank == 4) { in disable_err_thresholding()
654 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) in disable_err_thresholding()
657 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); in disable_err_thresholding()
682 unsigned int bank, block, cpu = smp_processor_id(); in mce_amd_feature_init() local
687 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in mce_amd_feature_init()
689 smca_configure(bank, cpu); in mce_amd_feature_init()
691 disable_err_thresholding(c, bank); in mce_amd_feature_init()
694 address = get_block_address(address, low, high, bank, block, cpu); in mce_amd_feature_init()
708 offset = prepare_threshold_block(bank, block, address, offset, high); in mce_amd_feature_init()
722 bank_type = smca_get_bank_type(m->extcpu, m->bank); in amd_mce_is_memory_error()
726 return m->bank == 4 && xec == 0x8; in amd_mce_is_memory_error()
729 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) in __log_error() argument
737 m.bank = bank; in __log_error()
747 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); in __log_error()
750 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); in __log_error()
769 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) in _log_error_bank() argument
780 __log_error(bank, status, addr, misc); in _log_error_bank()
787 static bool _log_error_deferred(unsigned int bank, u32 misc) in _log_error_deferred() argument
789 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), in _log_error_deferred()
790 mca_msr_reg(bank, MCA_ADDR), misc)) in _log_error_deferred()
801 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); in _log_error_deferred()
814 static void log_error_deferred(unsigned int bank) in log_error_deferred() argument
816 if (_log_error_deferred(bank, 0)) in log_error_deferred()
823 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), in log_error_deferred()
824 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); in log_error_deferred()
830 unsigned int bank; in amd_deferred_error_interrupt() local
832 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) in amd_deferred_error_interrupt()
833 log_error_deferred(bank); in amd_deferred_error_interrupt()
836 static void log_error_thresholding(unsigned int bank, u64 misc) in log_error_thresholding() argument
838 _log_error_deferred(bank, misc); in log_error_thresholding()
856 log_error_thresholding(block->bank, ((u64)high << 32) | low); in log_and_reset_block()
872 unsigned int bank, cpu = smp_processor_id(); in amd_threshold_interrupt() local
875 * Validate that the threshold bank has been initialized already. The in amd_threshold_interrupt()
882 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in amd_threshold_interrupt()
883 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) in amd_threshold_interrupt()
886 first_block = bp[bank]->blocks; in amd_threshold_interrupt()
1040 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) in get_name() argument
1045 if (b && bank == 4) in get_name()
1048 return th_names[bank]; in get_name()
1051 bank_type = smca_get_bank_type(cpu, bank); in get_name()
1066 per_cpu(smca_banks, cpu)[bank].sysfs_id); in get_name()
1071 unsigned int bank, unsigned int block, in allocate_threshold_blocks() argument
1078 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) in allocate_threshold_blocks()
1100 b->bank = bank; in allocate_threshold_blocks()
1104 b->interrupt_capable = lvt_interrupt_supported(bank, high); in allocate_threshold_blocks()
1122 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); in allocate_threshold_blocks()
1126 address = get_block_address(address, low, high, bank, ++block, cpu); in allocate_threshold_blocks()
1130 err = allocate_threshold_blocks(cpu, tb, bank, block, address); in allocate_threshold_blocks()
1172 unsigned int bank) in threshold_create_bank() argument
1177 const char *name = get_name(cpu, bank, NULL); in threshold_create_bank()
1183 if (is_shared_bank(bank)) { in threshold_create_bank()
1194 bp[bank] = b; in threshold_create_bank()
1209 /* Associate the bank with the per-CPU MCE device */ in threshold_create_bank()
1216 if (is_shared_bank(bank)) { in threshold_create_bank()
1227 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); in threshold_create_bank()
1231 bp[bank] = b; in threshold_create_bank()
1247 static void deallocate_threshold_blocks(struct threshold_bank *bank) in deallocate_threshold_blocks() argument
1251 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { in deallocate_threshold_blocks()
1256 kobject_put(&bank->blocks->kobj); in deallocate_threshold_blocks()
1270 static void threshold_remove_bank(struct threshold_bank *bank) in threshold_remove_bank() argument
1274 if (!bank->blocks) in threshold_remove_bank()
1277 if (!bank->shared) in threshold_remove_bank()
1280 if (!refcount_dec_and_test(&bank->cpus)) { in threshold_remove_bank()
1281 __threshold_remove_blocks(bank); in threshold_remove_bank()
1285 * The last CPU on this node using the shared bank is going in threshold_remove_bank()
1286 * away, remove that bank now. in threshold_remove_bank()
1293 deallocate_threshold_blocks(bank); in threshold_remove_bank()
1296 kobject_put(bank->kobj); in threshold_remove_bank()
1297 kfree(bank); in threshold_remove_bank()
1302 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); in __threshold_remove_device() local
1304 for (bank = 0; bank < numbanks; bank++) { in __threshold_remove_device()
1305 if (!bp[bank]) in __threshold_remove_device()
1308 threshold_remove_bank(bp[bank]); in __threshold_remove_device()
1309 bp[bank] = NULL; in __threshold_remove_device()
1344 unsigned int numbanks, bank; in mce_threshold_create_device() local
1360 for (bank = 0; bank < numbanks; ++bank) { in mce_threshold_create_device()
1361 if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) in mce_threshold_create_device()
1363 err = threshold_create_bank(bp, cpu, bank); in mce_threshold_create_device()