Lines Matching full:bank
54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
59 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
63 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
65 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
83 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
98 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
100 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
102 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
104 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
111 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_type() local
114 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
142 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
145 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
152 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_request_resources() local
153 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
158 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
160 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
162 bank->name, irqd->hwirq); in exynos_irq_request_resources()
166 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
170 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
172 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
175 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
177 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
184 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_release_resources() local
185 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
189 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
193 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
195 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
198 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
200 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
202 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
246 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq() local
250 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
256 bank += (group - 1); in exynos_eint_gpio_irq()
258 ret = generic_handle_domain_irq(bank->irq_domain, pin); in exynos_eint_gpio_irq()
278 struct samsung_pin_bank *bank; in exynos_eint_gpio_init() local
295 bank = d->pin_banks; in exynos_eint_gpio_init()
296 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
297 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
300 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
301 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
302 if (!bank->irq_chip) { in exynos_eint_gpio_init()
306 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
308 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_gpio_init()
309 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
310 if (!bank->irq_domain) { in exynos_eint_gpio_init()
316 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
318 if (!bank->soc_priv) { in exynos_eint_gpio_init()
319 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
329 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
330 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
332 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
342 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_wkup_irq_set_wake() local
343 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
346 irqd->irq, bank->name, irqd->hwirq); in exynos_wkup_irq_set_wake()
364 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
386 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
478 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15() local
483 generic_handle_domain_irq(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
532 struct samsung_pin_bank *bank; in exynos_eint_wkup_init() local
553 bank = d->pin_banks; in exynos_eint_wkup_init()
554 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
555 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
558 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
560 if (!bank->irq_chip) { in exynos_eint_wkup_init()
564 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
566 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_wkup_init()
567 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
568 if (!bank->irq_domain) { in exynos_eint_wkup_init()
574 if (!fwnode_property_present(bank->fwnode, "interrupts")) { in exynos_eint_wkup_init()
575 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
581 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
588 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
589 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); in exynos_eint_wkup_init()
592 bank->name, idx); in exynos_eint_wkup_init()
596 weint_data[idx].bank = bank; in exynos_eint_wkup_init()
623 bank = d->pin_banks; in exynos_eint_wkup_init()
625 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
626 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
629 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
638 struct samsung_pin_bank *bank) in exynos_pinctrl_suspend_bank() argument
640 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank()
641 void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend_bank()
644 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
646 + 2 * bank->eint_offset); in exynos_pinctrl_suspend_bank()
648 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend_bank()
649 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend_bank()
650 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
652 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
653 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
654 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
655 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynos_pinctrl_suspend_bank()
660 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_suspend() local
664 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { in exynos_pinctrl_suspend()
665 if (bank->eint_type == EINT_TYPE_GPIO) in exynos_pinctrl_suspend()
666 exynos_pinctrl_suspend_bank(drvdata, bank); in exynos_pinctrl_suspend()
667 else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
669 irq_chip = bank->irq_chip; in exynos_pinctrl_suspend()
679 struct samsung_pin_bank *bank) in exynos_pinctrl_resume_bank() argument
681 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank()
682 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume_bank()
684 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
686 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume_bank()
687 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
689 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume_bank()
690 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
692 + 2 * bank->eint_offset + 4), save->eint_fltcon1); in exynos_pinctrl_resume_bank()
693 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
694 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
695 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume_bank()
698 + bank->eint_offset); in exynos_pinctrl_resume_bank()
700 + 2 * bank->eint_offset); in exynos_pinctrl_resume_bank()
702 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume_bank()
703 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
704 + bank->eint_offset); in exynos_pinctrl_resume_bank()
709 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_resume() local
712 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) in exynos_pinctrl_resume()
713 if (bank->eint_type == EINT_TYPE_GPIO) in exynos_pinctrl_resume()
714 exynos_pinctrl_resume_bank(drvdata, bank); in exynos_pinctrl_resume()