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/openbmc/linux/drivers/mtd/spi-nor/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
4 spi-nor-objs += atmel.o
5 spi-nor-objs += catalyst.o
6 spi-nor-objs += eon.o
7 spi-nor-objs += esmt.o
8 spi-nor-objs += everspin.o
9 spi-nor-objs += fujitsu.o
10 spi-nor-objs += gigadevice.o
11 spi-nor-objs += intel.o
[all …]
H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/mtd/spi-nor.h>
4 #include <linux/spi/spi.h>
5 #include <linux/spi/spi-mem.h>
13 struct spi_device *spi = to_spi_device(dev); in manufacturer_show() local
14 struct spi_mem *spimem = spi_get_drvdata(spi); in manufacturer_show()
15 struct spi_nor *nor = spi_mem_get_drvdata(spimem); in manufacturer_show() local
17 return sysfs_emit(buf, "%s\n", nor->manufacturer->name); in manufacturer_show()
24 struct spi_device *spi = to_spi_device(dev); in partname_show() local
25 struct spi_mem *spimem = spi_get_drvdata(spi); in partname_show()
[all …]
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Standard SPI NOR flash operations. */
155 /* Dual SPI */
161 /* Quad SPI */
167 /* Octal SPI */
180 /* Quad SPI */
185 /* Octal SPI */
195 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
201 * @opcode: the SPI command op code to erase the sector/block.
216 * struct spi_nor_erase_command - Used for non-uniform erases
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
23 #include <linux/spi/flash.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
49 * @nor: pointer to a 'struct spi_nor'
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, in spi_nor_get_cmd_ext() argument
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
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/openbmc/u-boot/drivers/spi/
H A DKconfig1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
16 typically use driver-private data instead of extending the
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
[all …]
H A Dcdns,xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Parshuram Thombare <pthombar@cadence.com>
14 The XSPI controller allows SPI protocol communication in
16 read/write access to slaves such as SPI-NOR flash.
19 - $ref: spi-controller.yaml#
23 const: cdns,xspi-nor
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/openbmc/linux/Documentation/driver-api/mtd/
H A Dspi-nor.rst2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
18 details of the SPI NOR protocol.
20 Part II - How does the framework work?
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/openbmc/u-boot/drivers/mtd/spi/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
6 obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
7 spi-nor-y := sf_probe.o spi-nor-ids.o
10 obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
12 spi-nor-y += spi-nor-tiny.o
14 spi-nor-y += spi-nor-core.o
17 spi-nor-y += spi-nor-core.o
20 obj-$(CONFIG_SPI_FLASH) += spi-nor.o
21 obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
22 obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
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H A Dspi-nor-tiny.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
22 #include <spi.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
40 if (op->data.dir == SPI_MEM_DATA_IN) in spi_nor_read_write_reg()
41 op->data.buf.in = buf; in spi_nor_read_write_reg()
43 op->data.buf.out = buf; in spi_nor_read_write_reg()
44 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
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H A Dspi-nor-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
22 #include <spi.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
38 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
39 * @nor: pointer to a 'struct spi_nor'
44 void spi_nor_setup_op(const struct spi_nor *nor, in spi_nor_setup_op() argument
48 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); in spi_nor_setup_op()
50 if (op->addr.nbytes) in spi_nor_setup_op()
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-spi-devices-spi-nor1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
22 What: /sys/bus/spi/devices/.../spi-nor/partname
25 Contact: linux-mtd@lists.infradead.org
26 Description: (RO) Part name of the SPI NOR flash.
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/openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 0 => to switch SPI0_CS0_FL1_L to secondary SPI Nor d…
18 # 1 => to switch SPI0_CS0_FL0_L to primary SPI Nor dev…
25 HOST_MTD=$(< /proc/mtd grep "pnor" | sed -n 's/^\(.*\):.*/\1/p')
26 if [ -n "$HOST_MTD" ];
28 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
31 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
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/openbmc/u-boot/include/linux/mtd/
H A Dspi-nor.h1 // SPDX-License-Identifier: GPL-2.0
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
37 * requires a 4-byte (32-bit) address.
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
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/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 1 => to switch SPI_CS0_L to primary SPI Nor device
18 # 0 => to switch SPI_CS0_L to second SPI Nor device
26 HOST_MTD=$(< /proc/mtd grep "pnor" | sed -n 's/^\(.*\):.*/\1/p')
27 if [ -n "$HOST_MTD" ];
29 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
32 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
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H A Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
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/openbmc/linux/include/linux/mtd/
H A Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
[all …]
/openbmc/linux/drivers/mtd/spi-nor/controllers/
H A Dnxp-spifi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
18 #include <linux/mtd/spi-nor.h>
21 #include <linux/spi/spi.h>
58 struct spi_nor nor; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
71 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
85 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
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/openbmc/u-boot/board/boundary/nitrogen6x/
H A DREADME.mx6qsabrelite1 U-Boot for the Freescale i.MX6q SabreLite board
4 This file contains information for the port of U-Boot to the Freescale
9 --------
11 To build U-Boot for the SabreLite board:
18 --------------------
20 The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
22 board will still boot from SPI NOR, but the loader will in turn request the
23 BootROM to load the U-Boot from SD card.
29 This is provided under a open-source 3-clause BSD license.
31 To following procedure can be used to update the SPI-NOR on the SabreLite
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
[all …]
/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
[all …]
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PA5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
[all …]

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