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/openbmc/u-boot/include/
H A Dstm32_rcc.h60 u32 cr; /* RCC clock control */
61 u32 pllcfgr; /* RCC PLL configuration */
62 u32 cfgr; /* RCC clock configuration */
63 u32 cir; /* RCC clock interrupt */
64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
68 u32 apb1rstr; /* RCC APB1 peripheral reset */
69 u32 apb2rstr; /* RCC APB2 peripheral reset */
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi141 clocks = <&rcc TIM2_K>;
162 clocks = <&rcc TIM3_K>;
183 clocks = <&rcc TIM4_K>;
204 clocks = <&rcc TIM5_K>;
225 clocks = <&rcc TIM6_K>;
241 clocks = <&rcc TIM7_K>;
257 clocks = <&rcc TIM12_K>;
278 clocks = <&rcc TIM13_K>;
299 clocks = <&rcc TIM14_K>;
320 clocks = <&rcc LPTIM1_K>;
[all …]
H A Dstm32f429.dtsi47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
H A Dstm32f746.dtsi51 #include <dt-bindings/mfd/stm32f7-rcc.h>
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
112 rcc: rcc@40023810 { label
115 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
[all …]
H A Dstm32h743.dtsi46 #include <dt-bindings/mfd/stm32h7-rcc.h>
70 rcc: rcc@58024400 { label
73 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
84 clocks = <&rcc USART1_CK>;
92 clocks = <&rcc USART2_CK>;
99 clocks = <&rcc TIM5_CK>;
110 clocks = <&rcc FMC_CK>;
129 clocks = <&rcc SDMMC1_CK>;
130 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
H A Dstm32mp15-ddr.dtsi16 clocks = <&rcc AXIDCG>,
17 <&rcc DDRC1>,
18 <&rcc DDRC2>,
19 <&rcc DDRPHYC>,
20 <&rcc DDRCAPB>,
21 <&rcc DDRPHYCAPB>;
H A Dstm32h743-pinctrl.dtsi59 clocks = <&rcc GPIOA_CK>;
68 clocks = <&rcc GPIOB_CK>;
77 clocks = <&rcc GPIOC_CK>;
86 clocks = <&rcc GPIOD_CK>;
95 clocks = <&rcc GPIOE_CK>;
104 clocks = <&rcc GPIOF_CK>;
113 clocks = <&rcc GPIOG_CK>;
122 clocks = <&rcc GPIOH_CK>;
131 clocks = <&rcc GPIOI_CK>;
140 clocks = <&rcc GPIOJ_CK>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32mp151.dtsi133 clocks = <&rcc TIM2_K>;
168 clocks = <&rcc TIM3_K>;
204 clocks = <&rcc TIM4_K>;
238 clocks = <&rcc TIM5_K>;
274 clocks = <&rcc TIM6_K>;
294 clocks = <&rcc TIM7_K>;
314 clocks = <&rcc TIM12_K>;
338 clocks = <&rcc TIM13_K>;
362 clocks = <&rcc TIM14_K>;
385 clocks = <&rcc LPTIM1_K>;
[all …]
H A Dstm32mp131.dtsi117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
278 clocks = <&rcc TIM7_K>;
297 clocks = <&rcc LPTIM1_K>;
340 clocks = <&rcc SPI2_K>;
341 resets = <&rcc SPI2_R>;
365 clocks = <&rcc SPI3_K>;
[all …]
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
23 rcc: rcc@40023800 {
26 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
35 The secondary index is the bit number within the RCC register bank, starting
36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
42 drivers of the RCC IP, macros are available to generate the index in
46 - include/dt-bindings/mfd/stm32f4-rcc.h
52 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
[all …]
H A Dst,stm32mp1.txt5 for RCC IP and on fixed clocks.
8 RCC CLOCK = st,stm32mp1-rcc-clk
11 The RCC IP is both a reset and a clock controller but this documentation only
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
27 with value equals to RCC clock specifier as defined in
34 with DIV coding defined in RCC associated register RCC_xxxDIVR
61 with DIV value as defined in RCC spec:
96 rcc: rcc@50000000 {
101 rcc_clk: rcc-clk@50000000 {
[all …]
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
33 rcc: rcc@58024400 {
36 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
127 clocks = <&rcc TIM5_CK>;
137 The index is the bit number within the RCC registers bank, starting from RCC
145 All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
151 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
[all …]
H A Dst,stm32mp1-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
59 - st,stm32mp1-rcc-secure
60 - st,stm32mp1-rcc
61 - st,stm32mp13-rcc
80 - st,stm32mp1-rcc-secure
81 - st,stm32mp13-rcc
113 rcc: rcc@50000000 {
[all …]
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml87 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
93 select RCC clock instead of ETH_REF_CLK.
109 #include <dt-bindings/mfd/stm32h7-rcc.h>
122 clocks = <&rcc ETHMAC>,
123 <&rcc ETHTX>,
124 <&rcc ETHRX>,
125 <&rcc ETHSTP>,
126 <&rcc ETHCK_K>;
143 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
159 clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
/openbmc/linux/drivers/clk/qcom/
H A Dclk-rpm.c257 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
261 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
263 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
267 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
270 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
278 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
282 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
284 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
288 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
291 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml113 #include <dt-bindings/mfd/stm32f7-rcc.h>
123 resets = <&rcc 277>;
124 clocks = <&rcc 0 149>;
128 #include <dt-bindings/mfd/stm32f7-rcc.h>
138 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
139 clocks = <&rcc 1 CLK_I2C1>;
143 #include <dt-bindings/mfd/stm32f7-rcc.h>
156 clocks = <&rcc I2C2_K>;
157 resets = <&rcc I2C2_R>;
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c38 /* RCC registers */
1171 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_ls_osc_set() argument
1174 u32 address = rcc + offset; in stm32mp1_ls_osc_set()
1182 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) in stm32mp1_hs_ocs_set() argument
1184 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
1187 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_osc_wait() argument
1191 u32 address = rcc + offset; in stm32mp1_osc_wait()
1209 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, in stm32mp1_lse_enable() argument
1215 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1218 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
[all …]
/openbmc/u-boot/drivers/misc/
H A Dstm32_rcc.c75 {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
76 {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
77 {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
78 {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
79 {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
84 .name = "stm32-rcc",

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