14549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 23d2d115aSPatrick Delaunay/* 33d2d115aSPatrick Delaunay * Copyright : STMicroelectronics 2018 43d2d115aSPatrick Delaunay */ 53d2d115aSPatrick Delaunay 63d2d115aSPatrick Delaunay/ { 73d2d115aSPatrick Delaunay soc { 83d2d115aSPatrick Delaunay ddr: ddr@0x5A003000{ 93d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 103d2d115aSPatrick Delaunay 113d2d115aSPatrick Delaunay compatible = "st,stm32mp1-ddr"; 123d2d115aSPatrick Delaunay 133d2d115aSPatrick Delaunay reg = <0x5A003000 0x550 143d2d115aSPatrick Delaunay 0x5A004000 0x234>; 153d2d115aSPatrick Delaunay 16*a674313cSPatrick Delaunay clocks = <&rcc AXIDCG>, 17*a674313cSPatrick Delaunay <&rcc DDRC1>, 18*a674313cSPatrick Delaunay <&rcc DDRC2>, 19*a674313cSPatrick Delaunay <&rcc DDRPHYC>, 20*a674313cSPatrick Delaunay <&rcc DDRCAPB>, 21*a674313cSPatrick Delaunay <&rcc DDRPHYCAPB>; 223d2d115aSPatrick Delaunay 233d2d115aSPatrick Delaunay clock-names = "axidcg", 243d2d115aSPatrick Delaunay "ddrc1", 253d2d115aSPatrick Delaunay "ddrc2", 263d2d115aSPatrick Delaunay "ddrphyc", 273d2d115aSPatrick Delaunay "ddrcapb", 283d2d115aSPatrick Delaunay "ddrphycapb"; 293d2d115aSPatrick Delaunay 303d2d115aSPatrick Delaunay st,mem-name = DDR_MEM_NAME; 313d2d115aSPatrick Delaunay st,mem-speed = <DDR_MEM_SPEED>; 323d2d115aSPatrick Delaunay st,mem-size = <DDR_MEM_SIZE>; 333d2d115aSPatrick Delaunay 343d2d115aSPatrick Delaunay st,ctl-reg = < 353d2d115aSPatrick Delaunay DDR_MSTR 363d2d115aSPatrick Delaunay DDR_MRCTRL0 373d2d115aSPatrick Delaunay DDR_MRCTRL1 383d2d115aSPatrick Delaunay DDR_DERATEEN 393d2d115aSPatrick Delaunay DDR_DERATEINT 403d2d115aSPatrick Delaunay DDR_PWRCTL 413d2d115aSPatrick Delaunay DDR_PWRTMG 423d2d115aSPatrick Delaunay DDR_HWLPCTL 433d2d115aSPatrick Delaunay DDR_RFSHCTL0 443d2d115aSPatrick Delaunay DDR_RFSHCTL3 453d2d115aSPatrick Delaunay DDR_CRCPARCTL0 463d2d115aSPatrick Delaunay DDR_ZQCTL0 473d2d115aSPatrick Delaunay DDR_DFITMG0 483d2d115aSPatrick Delaunay DDR_DFITMG1 493d2d115aSPatrick Delaunay DDR_DFILPCFG0 503d2d115aSPatrick Delaunay DDR_DFIUPD0 513d2d115aSPatrick Delaunay DDR_DFIUPD1 523d2d115aSPatrick Delaunay DDR_DFIUPD2 533d2d115aSPatrick Delaunay DDR_DFIPHYMSTR 543d2d115aSPatrick Delaunay DDR_ODTMAP 553d2d115aSPatrick Delaunay DDR_DBG0 563d2d115aSPatrick Delaunay DDR_DBG1 573d2d115aSPatrick Delaunay DDR_DBGCMD 583d2d115aSPatrick Delaunay DDR_POISONCFG 593d2d115aSPatrick Delaunay DDR_PCCFG 603d2d115aSPatrick Delaunay >; 613d2d115aSPatrick Delaunay 623d2d115aSPatrick Delaunay st,ctl-timing = < 633d2d115aSPatrick Delaunay DDR_RFSHTMG 643d2d115aSPatrick Delaunay DDR_DRAMTMG0 653d2d115aSPatrick Delaunay DDR_DRAMTMG1 663d2d115aSPatrick Delaunay DDR_DRAMTMG2 673d2d115aSPatrick Delaunay DDR_DRAMTMG3 683d2d115aSPatrick Delaunay DDR_DRAMTMG4 693d2d115aSPatrick Delaunay DDR_DRAMTMG5 703d2d115aSPatrick Delaunay DDR_DRAMTMG6 713d2d115aSPatrick Delaunay DDR_DRAMTMG7 723d2d115aSPatrick Delaunay DDR_DRAMTMG8 733d2d115aSPatrick Delaunay DDR_DRAMTMG14 743d2d115aSPatrick Delaunay DDR_ODTCFG 753d2d115aSPatrick Delaunay >; 763d2d115aSPatrick Delaunay 773d2d115aSPatrick Delaunay st,ctl-map = < 783d2d115aSPatrick Delaunay DDR_ADDRMAP1 793d2d115aSPatrick Delaunay DDR_ADDRMAP2 803d2d115aSPatrick Delaunay DDR_ADDRMAP3 813d2d115aSPatrick Delaunay DDR_ADDRMAP4 823d2d115aSPatrick Delaunay DDR_ADDRMAP5 833d2d115aSPatrick Delaunay DDR_ADDRMAP6 843d2d115aSPatrick Delaunay DDR_ADDRMAP9 853d2d115aSPatrick Delaunay DDR_ADDRMAP10 863d2d115aSPatrick Delaunay DDR_ADDRMAP11 873d2d115aSPatrick Delaunay >; 883d2d115aSPatrick Delaunay 893d2d115aSPatrick Delaunay st,ctl-perf = < 903d2d115aSPatrick Delaunay DDR_SCHED 913d2d115aSPatrick Delaunay DDR_SCHED1 923d2d115aSPatrick Delaunay DDR_PERFHPR1 933d2d115aSPatrick Delaunay DDR_PERFLPR1 943d2d115aSPatrick Delaunay DDR_PERFWR1 953d2d115aSPatrick Delaunay DDR_PCFGR_0 963d2d115aSPatrick Delaunay DDR_PCFGW_0 973d2d115aSPatrick Delaunay DDR_PCFGQOS0_0 983d2d115aSPatrick Delaunay DDR_PCFGQOS1_0 993d2d115aSPatrick Delaunay DDR_PCFGWQOS0_0 1003d2d115aSPatrick Delaunay DDR_PCFGWQOS1_0 1013d2d115aSPatrick Delaunay DDR_PCFGR_1 1023d2d115aSPatrick Delaunay DDR_PCFGW_1 1033d2d115aSPatrick Delaunay DDR_PCFGQOS0_1 1043d2d115aSPatrick Delaunay DDR_PCFGQOS1_1 1053d2d115aSPatrick Delaunay DDR_PCFGWQOS0_1 1063d2d115aSPatrick Delaunay DDR_PCFGWQOS1_1 1073d2d115aSPatrick Delaunay >; 1083d2d115aSPatrick Delaunay 1093d2d115aSPatrick Delaunay st,phy-reg = < 1103d2d115aSPatrick Delaunay DDR_PGCR 1113d2d115aSPatrick Delaunay DDR_ACIOCR 1123d2d115aSPatrick Delaunay DDR_DXCCR 1133d2d115aSPatrick Delaunay DDR_DSGCR 1143d2d115aSPatrick Delaunay DDR_DCR 1153d2d115aSPatrick Delaunay DDR_ODTCR 1163d2d115aSPatrick Delaunay DDR_ZQ0CR1 1173d2d115aSPatrick Delaunay DDR_DX0GCR 1183d2d115aSPatrick Delaunay DDR_DX1GCR 1193d2d115aSPatrick Delaunay DDR_DX2GCR 1203d2d115aSPatrick Delaunay DDR_DX3GCR 1213d2d115aSPatrick Delaunay >; 1223d2d115aSPatrick Delaunay 1233d2d115aSPatrick Delaunay st,phy-timing = < 1243d2d115aSPatrick Delaunay DDR_PTR0 1253d2d115aSPatrick Delaunay DDR_PTR1 1263d2d115aSPatrick Delaunay DDR_PTR2 1273d2d115aSPatrick Delaunay DDR_DTPR0 1283d2d115aSPatrick Delaunay DDR_DTPR1 1293d2d115aSPatrick Delaunay DDR_DTPR2 1303d2d115aSPatrick Delaunay DDR_MR0 1313d2d115aSPatrick Delaunay DDR_MR1 1323d2d115aSPatrick Delaunay DDR_MR2 1333d2d115aSPatrick Delaunay DDR_MR3 1343d2d115aSPatrick Delaunay >; 1353d2d115aSPatrick Delaunay 1363d2d115aSPatrick Delaunay st,phy-cal = < 1373d2d115aSPatrick Delaunay DDR_DX0DLLCR 1383d2d115aSPatrick Delaunay DDR_DX0DQTR 1393d2d115aSPatrick Delaunay DDR_DX0DQSTR 1403d2d115aSPatrick Delaunay DDR_DX1DLLCR 1413d2d115aSPatrick Delaunay DDR_DX1DQTR 1423d2d115aSPatrick Delaunay DDR_DX1DQSTR 1433d2d115aSPatrick Delaunay DDR_DX2DLLCR 1443d2d115aSPatrick Delaunay DDR_DX2DQTR 1453d2d115aSPatrick Delaunay DDR_DX2DQSTR 1463d2d115aSPatrick Delaunay DDR_DX3DLLCR 1473d2d115aSPatrick Delaunay DDR_DX3DQTR 1483d2d115aSPatrick Delaunay DDR_DX3DQSTR 1493d2d115aSPatrick Delaunay >; 1503d2d115aSPatrick Delaunay 1513d2d115aSPatrick Delaunay status = "okay"; 1523d2d115aSPatrick Delaunay }; 1533d2d115aSPatrick Delaunay }; 1543d2d115aSPatrick Delaunay}; 155