Lines Matching full:rcc
4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
23 rcc: rcc@40023800 {
26 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
35 The secondary index is the bit number within the RCC register bank, starting
36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
42 drivers of the RCC IP, macros are available to generate the index in
46 - include/dt-bindings/mfd/stm32f4-rcc.h
52 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
57 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
74 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
84 The index is the bit number within the RCC registers bank, starting from RCC
94 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;