38 /* RCC registers */
1171 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,  in stm32mp1_ls_osc_set()  argument
1174 	u32 address = rcc + offset;  in stm32mp1_ls_osc_set()
1182 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)  in stm32mp1_hs_ocs_set()  argument
1184 	writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));  in stm32mp1_hs_ocs_set()
1187 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,  in stm32mp1_osc_wait()  argument
1191 	u32 address = rcc + offset;  in stm32mp1_osc_wait()
1209 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,  in stm32mp1_lse_enable()  argument
1215 		setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);  in stm32mp1_lse_enable()
1218 		setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);  in stm32mp1_lse_enable()
1224 	value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)  in stm32mp1_lse_enable()
1233 		clrsetbits_le32(rcc + RCC_BDCR,  in stm32mp1_lse_enable()
1238 	stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);  in stm32mp1_lse_enable()
1241 static void stm32mp1_lse_wait(fdt_addr_t rcc)  in stm32mp1_lse_wait()  argument
1243 	stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);  in stm32mp1_lse_wait()
1246 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)  in stm32mp1_lsi_set()  argument
1248 	stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);  in stm32mp1_lsi_set()
1249 	stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);  in stm32mp1_lsi_set()
1252 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)  in stm32mp1_hse_enable()  argument
1255 		writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);  in stm32mp1_hse_enable()
1257 		writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);  in stm32mp1_hse_enable()
1259 	stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);  in stm32mp1_hse_enable()
1260 	stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);  in stm32mp1_hse_enable()
1263 		writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);  in stm32mp1_hse_enable()
1266 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)  in stm32mp1_csi_set()  argument
1268 	stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);  in stm32mp1_csi_set()
1269 	stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);  in stm32mp1_csi_set()
1272 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)  in stm32mp1_hsi_set()  argument
1274 	stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);  in stm32mp1_hsi_set()
1275 	stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);  in stm32mp1_hsi_set()
1278 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)  in stm32mp1_set_hsidiv()  argument
1280 	u32 address = rcc + RCC_OCRDYR;  in stm32mp1_set_hsidiv()
1284 	clrsetbits_le32(rcc + RCC_HSICFGR,  in stm32mp1_set_hsidiv()
1298 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)  in stm32mp1_hsidiv()  argument
1314 		return stm32mp1_set_hsidiv(rcc, hsidiv);  in stm32mp1_hsidiv()
1373 	fdt_addr_t rcc = priv->base;  in pll_config_output()  local
1382 	writel(value, rcc + pll[pll_id].pllxcfgr2);  in pll_config_output()
1389 	fdt_addr_t rcc = priv->base;  in pll_config()  local
1415 	writel(value, rcc + pll[pll_id].pllxcfgr1);  in pll_config()
1421 	       rcc + pll[pll_id].pllxfracr);  in pll_config()
1424 	setbits_le32(rcc + pll[pll_id].pllxfracr,  in pll_config()
1577 	fdt_addr_t rcc = priv->base;  in stm32mp1_clktree()  local
1626 		stm32mp1_lsi_set(rcc, 1);  in stm32mp1_clktree()
1638 		stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);  in stm32mp1_clktree()
1649 		stm32mp1_hse_enable(rcc, bypass, digbyp, css);  in stm32mp1_clktree()
1654 	stm32mp1_csi_set(rcc, 1);  in stm32mp1_clktree()
1669 		stm32mp1_hsidiv(rcc, priv->osc[_HSI]);  in stm32mp1_clktree()
1676 	writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);  in stm32mp1_clktree()
1677 	set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);  in stm32mp1_clktree()
1678 	set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);  in stm32mp1_clktree()
1679 	set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);  in stm32mp1_clktree()
1680 	set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);  in stm32mp1_clktree()
1681 	set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);  in stm32mp1_clktree()
1682 	set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);  in stm32mp1_clktree()
1683 	set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);  in stm32mp1_clktree()
1686 	writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);  in stm32mp1_clktree()
1727 		stm32mp1_lse_wait(rcc);  in stm32mp1_clktree()
1766 		stm32mp1_hsi_set(rcc, 0);  in stm32mp1_clktree()