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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dfsl,spi-fsl-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Quad Serial Peripheral Interface (QuadSPI)
10 - Han Xu <han.xu@nxp.com>
13 - $ref: spi-controller.yaml#
18 - enum:
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
[all …]
H A Datmel,quadspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/atmel,quadspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tudor Ambarus <tudor.ambarus@linaro.org>
13 - $ref: spi-controller.yaml#
18 - atmel,sama5d2-qspi
19 - microchip,sam9x60-qspi
20 - microchip,sama7g5-qspi
21 - microchip,sama7g5-ospi
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 memory@80000000 {
15 device_type = "memory";
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
24 #interrupt-cells = <3>;
[all …]
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 memory@80000000 {
15 device_type = "memory";
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
[all …]
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
10 interrupt-parent = <&gic>;
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <100000000>;
16 clock-output-names = "sysclk";
19 gic: interrupt-controller@1400000 {
20 compatible = "arm,gic-400";
21 #interrupt-cells = <3>;
22 interrupt-controller;
[all …]
H A Dvf.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "simple-bus";
33 aips0: aips-bus@40000000 {
34 compatible = "fsl,aips-bus", "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
41 compatible = "fsl,vf610-lpuart";
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2014-2015, Freescale Semiconductor
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
[all …]
H A Dls1021a.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
45 compatible = "arm,armv7-timer";
53 compatible = "arm,cortex-a7-pmu";
[all …]
H A Dfsl-imx8mq.dtsi16 #include "fsl-imx8-ca53.dtsi"
17 #include <dt-bindings/clock/imx8mq-clock.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/input/input.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/pinctrl/pins-imx8mq.h>
22 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&gpc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
H A Dimx7ulp.dtsi2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <dt-bindings/clock/imx7ulp-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx7ulp-pinfunc.h"
16 interrupt-parent = <&intc>;
37 #address-cells = <1>;
38 #size-cells = <0>;
41 compatible = "arm,cortex-a7";
47 reserved-memory {
[all …]
H A Dimx6sx.dtsi9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
63 operating-points = <
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-fsl-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Freescale QuadSPI driver.
18 * Based on the original fsl-quadspi.c SPI NOR driver:
42 #include <linux/spi/spi-mem.h>
158 #define LUT_PAD(x) (fls(x) - 1)
164 * ---------------------------------------------------
166 * ---------------------------------------------------
188 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
279 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian()
284 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock()
[all …]
/openbmc/u-boot/board/freescale/ls2080ardb/
H A Dls2080ardb.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <fsl-mc/fsl_mc.h>
46 if (gd->flags & GD_FLG_RELOC) in get_qixis_addr()
68 printf("Board: %s-RDB, ", buf); in checkboard()
196 return -1; in config_board_mux()
213 gd->env_addr = (ulong)&default_environment[0]; in board_init()
254 u32 svr = gur_in32(&gur->svr); in misc_init_r()
299 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); in detail_board_ddr_info()
302 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { in detail_board_ddr_info()
303 puts("\nDP-DDR "); in detail_board_ddr_info()
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
12 compatible = "altr,niosii-max10";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 u-boot,dm-pre-reloc;
23 compatible = "altr,nios2-1.1";
25 interrupt-controller;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
[all …]
/openbmc/u-boot/board/freescale/ls1088a/
H A Dls1088a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
16 #include <fsl-mc/fsl_mc.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
137 regs_info->regs = ifc_cfg_qspi_nor_boot; in ifc_cfg_boot_info()
139 regs_info->regs = ifc_cfg_ifc_nor_boot; in ifc_cfg_boot_info()
141 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; in ifc_cfg_boot_info()
160 if (gd->flags & GD_FLG_RELOC) in get_qixis_addr()
198 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); in fixup_ls1088ardb_pb_banner()
216 printf("Board: LS1088A-QDS, "); in checkboard()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
/openbmc/u-boot/drivers/spi/
H A Dfsl_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013-2015 Freescale Semiconductor, Inc.
69 /* Used for Spansion S25FS-S family flash only. */
73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
88 * struct fsl_qspi_platdata - platform data for Freescale QSPI
93 * @amba_base: Base address of QSPI memory mapping
94 * @amba_total_size: size of QSPI memory mapping
109 * struct fsl_qspi_priv - private data for Freescale QSPI
116 * @amba_base: Base address of QSPI memory mapping of every CS
117 * @amba_total_size: size of QSPI memory mapping
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/linux/drivers/mtd/spi-nor/controllers/
H A Dnxp-spifi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Based on Freescale QuadSPI driver:
18 #include <linux/mtd/spi-nor.h>
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
71 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
85 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
94 if (!spifi->memory_mode) in nxp_spifi_set_memory_mode_off()
99 dev_err(spifi->dev, "unable to enter command mode\n"); in nxp_spifi_set_memory_mode_off()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
[all …]

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