1STM32 QSPI controller device tree bindings
2--------------------------------------------
3
4Required properties:
5- compatible		: should be "st,stm32-qspi".
6- reg			: 1. Physical base address and size of SPI registers map.
7			  2. Physical base address & size of mapped NOR Flash.
8- spi-max-frequency	: Max supported spi frequency.
9- status		: enable in requried dts.
10
11Connected flash properties
12--------------------------
13- spi-max-frequency	: Max supported spi frequency.
14- spi-tx-bus-width	: Bus width (number of lines) for writing (1-4)
15- spi-rx-bus-width	: Bus width (number of lines) for reading (1-4)
16- memory-map		: Address and size for memory-mapping the flash
17
18Example:
19	qspi: quadspi@A0001000 {
20		compatible = "st,stm32-qspi";
21		#address-cells = <1>;
22		#size-cells = <0>;
23		reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
24		reg-names = "QuadSPI", "QuadSPI-memory";
25		interrupts = <92>;
26		spi-max-frequency = <108000000>;
27		status = "okay";
28
29		qflash0: n25q128a {
30			#address-cells = <1>;
31			#size-cells = <1>;
32			compatible = "micron,n25q128a13", "spi-flash";
33			spi-max-frequency = <108000000>;
34			spi-tx-bus-width = <4>;
35			spi-rx-bus-width = <4>;
36			memory-map = <0x90000000 0x1000000>;
37			reg = <0>;
38		};
39	};
40