1*b1a8de7eSMichael KurzSTM32 QSPI controller device tree bindings 2*b1a8de7eSMichael Kurz-------------------------------------------- 3*b1a8de7eSMichael Kurz 4*b1a8de7eSMichael KurzRequired properties: 5*b1a8de7eSMichael Kurz- compatible : should be "st,stm32-qspi". 6*b1a8de7eSMichael Kurz- reg : 1. Physical base address and size of SPI registers map. 7*b1a8de7eSMichael Kurz 2. Physical base address & size of mapped NOR Flash. 8*b1a8de7eSMichael Kurz- spi-max-frequency : Max supported spi frequency. 9*b1a8de7eSMichael Kurz- status : enable in requried dts. 10*b1a8de7eSMichael Kurz 11*b1a8de7eSMichael KurzConnected flash properties 12*b1a8de7eSMichael Kurz-------------------------- 13*b1a8de7eSMichael Kurz- spi-max-frequency : Max supported spi frequency. 14*b1a8de7eSMichael Kurz- spi-tx-bus-width : Bus width (number of lines) for writing (1-4) 15*b1a8de7eSMichael Kurz- spi-rx-bus-width : Bus width (number of lines) for reading (1-4) 16*b1a8de7eSMichael Kurz- memory-map : Address and size for memory-mapping the flash 17*b1a8de7eSMichael Kurz 18*b1a8de7eSMichael KurzExample: 19*b1a8de7eSMichael Kurz qspi: quadspi@A0001000 { 20*b1a8de7eSMichael Kurz compatible = "st,stm32-qspi"; 21*b1a8de7eSMichael Kurz #address-cells = <1>; 22*b1a8de7eSMichael Kurz #size-cells = <0>; 23*b1a8de7eSMichael Kurz reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 24*b1a8de7eSMichael Kurz reg-names = "QuadSPI", "QuadSPI-memory"; 25*b1a8de7eSMichael Kurz interrupts = <92>; 26*b1a8de7eSMichael Kurz spi-max-frequency = <108000000>; 27*b1a8de7eSMichael Kurz status = "okay"; 28*b1a8de7eSMichael Kurz 29*b1a8de7eSMichael Kurz qflash0: n25q128a { 30*b1a8de7eSMichael Kurz #address-cells = <1>; 31*b1a8de7eSMichael Kurz #size-cells = <1>; 32*b1a8de7eSMichael Kurz compatible = "micron,n25q128a13", "spi-flash"; 33*b1a8de7eSMichael Kurz spi-max-frequency = <108000000>; 34*b1a8de7eSMichael Kurz spi-tx-bus-width = <4>; 35*b1a8de7eSMichael Kurz spi-rx-bus-width = <4>; 36*b1a8de7eSMichael Kurz memory-map = <0x90000000 0x1000000>; 37*b1a8de7eSMichael Kurz reg = <0>; 38*b1a8de7eSMichael Kurz }; 39*b1a8de7eSMichael Kurz }; 40