drivers/spi/fsl_qspi.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
69 /* Used for Spansion S25FS-S family flash only. */
73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
88  * struct fsl_qspi_platdata - platform data for Freescale QSPI
93  * @amba_base: Base address of QSPI memory mapping
94  * @amba_total_size: size of QSPI memory mapping
109  * struct fsl_qspi_priv - private data for Freescale QSPI
116  * @amba_base: Base address of QSPI memory mapping of every CS
117  * @amba_total_size: size of QSPI memory mapping
118  * @cur_amba_base: Base address of QSPI memory mapping of current CS
158 		val = qspi_read32(priv->flags, &priv->regs->sr);  in is_controller_busy()
164 	} while (--retry);  in is_controller_busy()
166 	return -ETIMEDOUT;  in is_controller_busy()
182 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_set_lut()
186 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
187 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);  in qspi_set_lut()
191 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |  in qspi_set_lut()
193 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
194 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
195 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
200 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
206 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
211 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
217 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
221 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
222 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
226 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |  in qspi_set_lut()
229 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
230 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
231 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
236 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |  in qspi_set_lut()
241 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
246 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
251 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
252 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
253 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
257 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
260 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
261 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
262 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
267 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |  in qspi_set_lut()
272 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
277 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
288 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |  in qspi_set_lut()
291 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
295 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
296 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
300 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |  in qspi_set_lut()
303 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
304 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
305 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
309 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |  in qspi_set_lut()
320 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |  in qspi_set_lut()
325 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |  in qspi_set_lut()
330 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |  in qspi_set_lut()
335 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |  in qspi_set_lut()
342 	 * Used for Spansion S25FS-S family flash only.  in qspi_set_lut()
345 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
349 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
356 	 * Used for Spansion S25FS-S family flash only.  in qspi_set_lut()
359 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
363 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
367 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
368 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);  in qspi_set_lut()
380 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_invalid()
383 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_invalid()
385 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
394 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
400 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_read()
404 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_read()
406 	qspi_write32(priv->flags, &regs->mcr,  in qspi_ahb_read()
410 	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);  in qspi_ahb_read()
414 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_ahb_read()
420 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_enable_ddr_mode()
422 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_enable_ddr_mode()
424 	qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);  in qspi_enable_ddr_mode()
427 	reg2 = qspi_read32(priv->flags, &regs->smpr);  in qspi_enable_ddr_mode()
430 	qspi_write32(priv->flags, &regs->smpr, reg2);  in qspi_enable_ddr_mode()
437 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_enable_ddr_mode()
455 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_init_ahb_read()
458 	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
459 	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
460 	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
461 	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |  in qspi_init_ahb_read()
465 	qspi_write32(priv->flags, &regs->buf0ind, 0);  in qspi_init_ahb_read()
466 	qspi_write32(priv->flags, &regs->buf1ind, 0);  in qspi_init_ahb_read()
467 	qspi_write32(priv->flags, &regs->buf2ind, 0);  in qspi_init_ahb_read()
473 	qspi_write32(priv->flags, &regs->bfgencr,  in qspi_init_ahb_read()
485 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdbank()
488 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdbank()
489 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
492 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdbank()
494 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdbank()
496 	if (priv->cur_seqid == QSPI_CMD_BRRD)  in qspi_op_rdbank()
501 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdbank()
505 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdbank()
511 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdbank()
513 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdbank()
516 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
517 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdbank()
523 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdbank()
529 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdid()
533 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdid()
534 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdid()
537 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdid()
539 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdid()
541 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdid()
543 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdid()
550 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdid()
552 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_rdid()
556 			len -= size;  in qspi_op_rdid()
562 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdid()
568 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_read()
574 	if (priv->cur_seqid == QSPI_CMD_RDAR)  in qspi_op_read()
579 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_read()
580 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
583 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_read()
585 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_read()
590 		qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_read()
595 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_read()
598 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_read()
602 		len -= size;  in qspi_op_read()
606 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_read()
613 			size -= 4;  in qspi_op_read()
616 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
617 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_read()
621 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_read()
626 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_write()
631 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_write()
632 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
635 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_write()
641 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
643 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
646 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
648 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
651 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_write()
653 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_write()
656 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
657 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_write()
663 	if (priv->cur_seqid == QSPI_CMD_WRAR)  in qspi_op_write()
666 	if (priv->cur_seqid == QSPI_CMD_BRWR)  in qspi_op_write()
668 	else if (priv->cur_seqid == QSPI_CMD_WREAR)  in qspi_op_write()
672 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_write()
674 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_write()
689 		qspi_write32(priv->flags, &regs->tbdr, data);  in qspi_op_write()
693 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
695 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
698 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_write()
703 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdsr()
706 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdsr()
707 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
710 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdsr()
712 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdsr()
714 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdsr()
716 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdsr()
722 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdsr()
724 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdsr()
727 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
728 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdsr()
734 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdsr()
739 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_erase()
743 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_erase()
744 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_erase()
747 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_erase()
749 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_erase()
750 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_erase()
752 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
754 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
757 	if (priv->cur_seqid == QSPI_CMD_SE) {  in qspi_op_erase()
758 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
760 	} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {  in qspi_op_erase()
761 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
764 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
767 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_erase()
781 			priv->cur_seqid = *(u8 *)dout;  in qspi_xfer()
786 			priv->sf_addr = wr_sfaddr;  in qspi_xfer()
791 		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||  in qspi_xfer()
792 		    priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
793 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
794 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
795 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {  in qspi_xfer()
796 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
798 		} else if (priv->cur_seqid == QSPI_CMD_PP ||  in qspi_xfer()
799 			   priv->cur_seqid == QSPI_CMD_WRAR) {  in qspi_xfer()
801 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||  in qspi_xfer()
802 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {  in qspi_xfer()
810 		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {  in qspi_xfer()
816 		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
818 		} else if (priv->cur_seqid == QSPI_CMD_RDID)  in qspi_xfer()
820 		else if (priv->cur_seqid == QSPI_CMD_RDSR)  in qspi_xfer()
823 		else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||  in qspi_xfer()
824 			 (priv->cur_seqid == QSPI_CMD_RDEAR)) {  in qspi_xfer()
825 			priv->sf_addr = 0;  in qspi_xfer()
832 	if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
833 	    (priv->cur_seqid == QSPI_CMD_PP) ||  in qspi_xfer()
834 	    (priv->cur_seqid == QSPI_CMD_BE_4K) ||  in qspi_xfer()
835 	    (priv->cur_seqid == QSPI_CMD_WREAR) ||  in qspi_xfer()
836 	    (priv->cur_seqid == QSPI_CMD_BRWR))  in qspi_xfer()
847 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in qspi_module_disable()
852 	qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);  in qspi_module_disable()
859 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);  in qspi_cfg_smpr()
862 	qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);  in qspi_cfg_smpr()
869 	slave->max_write_size = TX_BUFFER_SIZE;  in fsl_qspi_child_pre_probe()
883 	dm_spi_bus = bus->uclass_priv;  in fsl_qspi_probe()
885 	dm_spi_bus->max_hz = plat->speed_hz;  in fsl_qspi_probe()
887 	priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;  in fsl_qspi_probe()
888 	priv->flags = plat->flags;  in fsl_qspi_probe()
890 	priv->speed_hz = plat->speed_hz;  in fsl_qspi_probe()
892 	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.  in fsl_qspi_probe()
893 	 * AMBA memory zone should be located on the 0~4GB space  in fsl_qspi_probe()
896 	priv->amba_base[0] = (u32)plat->amba_base;  in fsl_qspi_probe()
897 	priv->amba_total_size = (u32)plat->amba_total_size;  in fsl_qspi_probe()
898 	priv->flash_num = plat->flash_num;  in fsl_qspi_probe()
899 	priv->num_chipselect = plat->num_chipselect;  in fsl_qspi_probe()
909 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in fsl_qspi_probe()
915 	qspi_write32(priv->flags, &priv->regs->mcr,  in fsl_qspi_probe()
923 	 * Assign AMBA memory zone for every chipselect  in fsl_qspi_probe()
924 	 * QuadSPI has two channels, every channel has two chipselects.  in fsl_qspi_probe()
925 	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided  in fsl_qspi_probe()
928 	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided  in fsl_qspi_probe()
932 	amba_size_per_chip = priv->amba_total_size >>  in fsl_qspi_probe()
933 			     (priv->num_chipselect >> 1);  in fsl_qspi_probe()
934 	for (i = 1 ; i < priv->num_chipselect ; i++)  in fsl_qspi_probe()
935 		priv->amba_base[i] =  in fsl_qspi_probe()
936 			amba_size_per_chip + priv->amba_base[i - 1];  in fsl_qspi_probe()
939 	 * Any read access to non-implemented addresses will provide  in fsl_qspi_probe()
944 	 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,  in fsl_qspi_probe()
946 	 * that the complete memory map is assigned to only one flash device.  in fsl_qspi_probe()
948 	qspi_write32(priv->flags, &priv->regs->sfa1ad,  in fsl_qspi_probe()
949 		     priv->amba_base[0] + amba_size_per_chip);  in fsl_qspi_probe()
950 	switch (priv->num_chipselect) {  in fsl_qspi_probe()
954 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
955 			     priv->amba_base[1]);  in fsl_qspi_probe()
956 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
957 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
958 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
959 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
962 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
963 			     priv->amba_base[2]);  in fsl_qspi_probe()
964 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
965 			     priv->amba_base[3]);  in fsl_qspi_probe()
966 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
967 			     priv->amba_base[3] + amba_size_per_chip);  in fsl_qspi_probe()
971 		      priv->num_chipselect);  in fsl_qspi_probe()
973 		return -EINVAL;  in fsl_qspi_probe()
990 	struct fsl_qspi_platdata *plat = bus->platdata;  in fsl_qspi_ofdata_to_platdata()
991 	const void *blob = gd->fdt_blob;  in fsl_qspi_ofdata_to_platdata()
995 	if (fdtdec_get_bool(blob, node, "big-endian"))  in fsl_qspi_ofdata_to_platdata()
996 		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;  in fsl_qspi_ofdata_to_platdata()
998 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",  in fsl_qspi_ofdata_to_platdata()
999 				     "QuadSPI", &res_regs);  in fsl_qspi_ofdata_to_platdata()
1002 		return -ENOMEM;  in fsl_qspi_ofdata_to_platdata()
1004 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",  in fsl_qspi_ofdata_to_platdata()
1005 				     "QuadSPI-memory", &res_mem);  in fsl_qspi_ofdata_to_platdata()
1008 		return -ENOMEM;  in fsl_qspi_ofdata_to_platdata()
1017 		return -ENODEV;  in fsl_qspi_ofdata_to_platdata()
1020 	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",  in fsl_qspi_ofdata_to_platdata()
1022 	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",  in fsl_qspi_ofdata_to_platdata()
1025 	plat->reg_base = res_regs.start;  in fsl_qspi_ofdata_to_platdata()
1026 	plat->amba_base = res_mem.start;  in fsl_qspi_ofdata_to_platdata()
1027 	plat->amba_total_size = res_mem.end - res_mem.start + 1;  in fsl_qspi_ofdata_to_platdata()
1028 	plat->flash_num = flash_num;  in fsl_qspi_ofdata_to_platdata()
1030 	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",  in fsl_qspi_ofdata_to_platdata()
1032 	      (u64)plat->reg_base,  in fsl_qspi_ofdata_to_platdata()
1033 	      (u64)plat->amba_base,  in fsl_qspi_ofdata_to_platdata()
1034 	      (u64)plat->amba_total_size,  in fsl_qspi_ofdata_to_platdata()
1035 	      plat->speed_hz,  in fsl_qspi_ofdata_to_platdata()
1036 	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"  in fsl_qspi_ofdata_to_platdata()
1048 	bus = dev->parent;  in fsl_qspi_xfer()
1061 	bus = dev->parent;  in fsl_qspi_claim_bus()
1072 	priv->cur_amba_base = priv->amba_base[slave_plat->cs];  in fsl_qspi_claim_bus()
1084 	bus = dev->parent;  in fsl_qspi_release_bus()
1113 	{ .compatible = "fsl,vf610-qspi" },
1114 	{ .compatible = "fsl,imx6sx-qspi" },
1115 	{ .compatible = "fsl,imx6ul-qspi" },
1116 	{ .compatible = "fsl,imx7d-qspi" },