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/openbmc/u-boot/drivers/power/
H A Dexynos-tmu.c6 * EXYNOS - Thermal Management Unit
17 * MA 02111-1307 USA
64 /* Pre-defined values and thresholds for calibration of current temperature */
66 /* pre-defined temperature thresholds */
68 /* pre-defined efuse range minimum value */
70 /* pre-defined efuse value for temperature calibration */
72 /* pre-defined efuse range maximum value */
84 /* pre-defined values for calibration and thresholds */
86 /* value required for triminfo_25 calibration */
88 /* value required for triminfo_85 calibration */
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600-pfr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
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H A Dast2600-dcscm.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-evb.dts"
7 model = "AST2600 DC-SCM";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_fmcquad_default>;
15 timing-calibration-disabled;
16 num-cs = <1>;
20 spi-max-frequency = <12500000>;
21 spi-tx-bus-width = <4>;
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/openbmc/linux/drivers/iio/adc/
H A Dqcom-spmi-vadc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
10 #include <linux/iio/adc/qcom-vadc-common.h>
23 #include <dt-bindings/iio/qcom,spmi-vadc.h>
76 * struct vadc_channel_prop - VADC channel property.
78 * @calibration: calibration type.
91 enum vadc_calibration calibration; member
101 * struct vadc_priv - VADC private structure.
111 * @graph: store parameters for calibration.
141 return regmap_bulk_read(vadc->regmap, vadc->base + offset, data, 1); in vadc_read()
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H A Dqcom-pm8xxx-xoadc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * specific-purpose and general purpose ADC converters and channels.
13 #include <linux/iio/adc/qcom-vadc-common.h>
27 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
28 * drivers/misc/pmic8058-xoadc.c
29 * drivers/hwmon/pm8xxx-adc.c
124 * proper reference points for calibration.
155 * struct xoadc_channel - encodes channel properties and defaults
162 * @prescale: the channels have hard-coded prescale ratios defined
185 * struct xoadc_variant - encodes the XOADC variant characteristics
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H A Dstm32-adc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
16 #include <linux/iio/timer/stm32-lptim-trigger.h>
17 #include <linux/iio/timer/stm32-timer-trigger.h>
26 #include <linux/nvmem-consumer.h>
31 #include "stm32-adc-core.h"
33 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
58 /* extsel - trigger mux selection value */
84 STM32_ADC_INT_CH_NONE = -1,
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/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-spmi-adc-tm-hc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 const: qcom,spmi-adc-tm-hc
21 "#thermal-sensor-cells":
27 "#address-cells":
30 "#size-cells":
33 qcom,avg-samples:
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H A Dqcom-spmi-adc-tm5.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 - qcom,spmi-adc-tm5
15 - qcom,spmi-adc-tm5-gen2
16 - qcom,adc-tm7 # Incomplete / subject to change
24 "#thermal-sensor-cells":
30 "#address-cells":
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H A Dqcom-tsens.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 ---
5 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Amit Kucheria <amitk@kernel.org>
22 - description: msm8960 TSENS based
24 - enum:
25 - qcom,ipq8064-tsens
26 - qcom,msm8960-tsens
28 - description: v0.1 of TSENS
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/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kalle Valo <kvalo@kernel.org>
18 - qcom,ath10k # SDIO-based devices
19 - qcom,ipq4019-wifi
20 - qcom,wcn3990-wifi # SNoC-based devices
25 reg-names:
27 - const: membase
33 interrupt-names:
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-ap120c-ac.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
8 model = "ALFA Network AP120C-AC";
9 compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";
16 stdout-path = "serial0:115200n8";
20 compatible = "gpio-keys";
22 key-reset {
35 drive-strength = <16>;
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - drv260x Haptics driver family
10 - Andrew Davis <afd@ti.com>
15 - ti,drv2604
16 - ti,drv2605
17 - ti,drv2605l
22 vbat-supply:
30 (defined in include/dt-bindings/input/ti-drv260x.h)
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/openbmc/u-boot/board/keymile/kmp204x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
27 /* automatic calibration for nb of cycles between read and DQS pre */ in fsl_ddr_board_options()
28 popts->cpo_override = 0xFF; in fsl_ddr_board_options()
31 popts->write_data_delay = 4; in fsl_ddr_board_options()
33 popts->clk_adjust = 4; in fsl_ddr_board_options()
35 popts->twot_en = 0; in fsl_ddr_board_options()
38 popts->half_strength_driver_enable = 1; in fsl_ddr_board_options()
41 popts->wrlvl_override = 1; in fsl_ddr_board_options()
42 popts->wrlvl_sample = 0xf; in fsl_ddr_board_options()
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dfsl_mmdc.c1 // SPDX-License-Identifier: GPL-2.0+
22 timeout--; in set_wait_for_bits_clear()
34 out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); in mmdc_init()
37 out_be32(&mmdc->mdotc, priv->mdotc); in mmdc_init()
38 out_be32(&mmdc->mdcfg0, priv->mdcfg0); in mmdc_init()
39 out_be32(&mmdc->mdcfg1, priv->mdcfg1); in mmdc_init()
40 out_be32(&mmdc->mdcfg2, priv->mdcfg2); in mmdc_init()
43 out_be32(&mmdc->mdmisc, priv->mdmisc); in mmdc_init()
44 out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR); in mmdc_init()
45 out_be32(&mmdc->mdrwd, priv->mdrwd); in mmdc_init()
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/openbmc/linux/drivers/input/touchscreen/
H A Dimx6ul_tsc.c1 // SPDX-License-Identifier: GPL-2.0
111 reinit_completion(&tsc->completion); in imx6ul_adc_init()
113 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
118 if (tsc->average_enable) { in imx6ul_adc_init()
120 adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT; in imx6ul_adc_init()
123 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
125 /* enable calibration interrupt */ in imx6ul_adc_init()
128 writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); in imx6ul_adc_init()
130 /* start ADC calibration */ in imx6ul_adc_init()
131 adc_gc = readl(tsc->adc_regs + REG_ADC_GC); in imx6ul_adc_init()
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/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dcore.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
15 #include <linux/nvmem-consumer.h>
27 #include "wmi-ops.h"
55 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
56 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
464 * or 2x2 160Mhz, long-guard-interval.
514 * 1x1 160Mhz, long-guard-interval.
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/openbmc/linux/drivers/media/tuners/
H A Dfc0011.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
51 FC11_VCOCAL_RUN = 0, /* VCO calibration run */
52 FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
53 FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
54 FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
70 struct i2c_msg msg = { .addr = priv->addr, in fc0011_writereg()
73 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0011_writereg()
74 dev_err(&priv->i2c->dev, in fc0011_writereg()
77 return -EIO; in fc0011_writereg()
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/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dlink.c20 * TX polling - checks if the TX engine is stuck somewhere
28 if (sc->tx99_state) in ath_tx_complete_check()
32 txq = sc->tx.txq_map[i]; in ath_tx_complete_check()
35 if (txq->axq_depth) { in ath_tx_complete_check()
36 if (txq->axq_tx_inprogress) { in ath_tx_complete_check()
41 txq->axq_tx_inprogress = true; in ath_tx_complete_check()
49 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, in ath_tx_complete_check()
65 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, in ath_hw_check_work()
74 struct ath_common *common = ath9k_hw_common(sc->sc_ah); in ath_hw_check()
80 is_alive = ath9k_hw_check_alive(sc->sc_ah); in ath_hw_check()
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
42 u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
43 u32 ddr_lap_count; /* DDR Calibration Measured Value */
44 u32 ddr_cal_delay; /* DDR Calibration Delay Value */
78 #define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
116 #define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
144 #define CLK_UART(n) (1 << ((n) - 3))
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
37 /* DN Resistor calibration code parameters */
86 /* Calibration digital logic parameters */
190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
204 * struct xpsgtr_phy - representation of a lane
224 * struct xpsgtr_dev - representation of a ZynMP GT device
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsdrc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
62 * This structure holds a pre-computed set of register values for the
64 * intended to be pre-computed and specified in an array in the board-*.c
112 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
124 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
166 * become sub-optimal. The RFR value goes in the opposite direction. If you
170 * unlocked and their value needs run time calibration. A dynamic call is
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/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A DKconfig91 bool "Include dynamic DDR calibration routines"
95 Say "Y" if your board uses dynamic (per-boot) DDR calibration.
103 bool "Advantech dms-ba16"
126 bool "Support aristainetos2-revB"
139 bool "CM-FX6"
210 bool "Solid-run mx6 boards"
236 development and pre-production stages.
404 bool "PICO-IMX6UL-EMMC"
416 bool "platinum-picon"
420 bool "platinum-titanium"
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/openbmc/u-boot/include/
H A Dfsl_mmdc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
19 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
61 /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */

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