1 // SPDX-License-Identifier: GPL-2.0+
22 		timeout--;  in set_wait_for_bits_clear()
34 	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);  in mmdc_init()
37 	out_be32(&mmdc->mdotc, priv->mdotc);  in mmdc_init()
38 	out_be32(&mmdc->mdcfg0, priv->mdcfg0);  in mmdc_init()
39 	out_be32(&mmdc->mdcfg1, priv->mdcfg1);  in mmdc_init()
40 	out_be32(&mmdc->mdcfg2, priv->mdcfg2);  in mmdc_init()
43 	out_be32(&mmdc->mdmisc, priv->mdmisc);  in mmdc_init()
44 	out_be32(&mmdc->mpmur0,	MMDC_MPMUR0_FRC_MSR);  in mmdc_init()
45 	out_be32(&mmdc->mdrwd, priv->mdrwd);  in mmdc_init()
46 	out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);  in mmdc_init()
49 	out_be32(&mmdc->mdor, priv->mdor);  in mmdc_init()
53 	tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);  in mmdc_init()
54 	out_be32(&mmdc->mdctl, tmp);  in mmdc_init()
56 	out_be32(&mmdc->mdasp, priv->mdasp);  in mmdc_init()
58 	/* 6. perform a ZQ calibration - not needed here, doing in #8b */  in mmdc_init()
62 		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);  in mmdc_init()
64 		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);  in mmdc_init()
67 	/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */  in mmdc_init()
68 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
71 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
74 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
77 	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x19) |  in mmdc_init()
82 	/* 8b. ZQ calibration */  in mmdc_init()
83 	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
86 	set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,  in mmdc_init()
90 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |  in mmdc_init()
94 	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |  in mmdc_init()
97 	set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,  in mmdc_init()
102 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
104 	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);  in mmdc_init()
108 	/* 9b. read DQS gating calibration */  in mmdc_init()
109 	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
112 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
115 	out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);  in mmdc_init()
118 	if (priv->mprddlctl)  in mmdc_init()
119 		out_be32(&mmdc->mprddlctl, priv->mprddlctl);  in mmdc_init()
121 		out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);  in mmdc_init()
123 	set_wait_for_bits_clear(&mmdc->mpdgctrl0,  in mmdc_init()
127 	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |  in mmdc_init()
130 	/* 9c. read calibration */  in mmdc_init()
131 	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
133 	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |  in mmdc_init()
135 	out_be32(&mmdc->mppdcmpr2,  MPPDCMPR2_MPR_COMPARE_EN);  in mmdc_init()
136 	set_wait_for_bits_clear(&mmdc->mprddlhwctl,  in mmdc_init()
140 	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |  in mmdc_init()
143 	/* 10. configure power-down, self-refresh entry, exit parameters */  in mmdc_init()
144 	out_be32(&mmdc->mdpdc, priv->mdpdc);  in mmdc_init()
145 	out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);  in mmdc_init()
150 	set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,  in mmdc_init()
154 	out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);  in mmdc_init()