Lines Matching +full:pre +full:- +full:calibration

1 // SPDX-License-Identifier: GPL-2.0+
6  * Copyright 2009-2011 Freescale Semiconductor, Inc.
27 	/* automatic calibration for nb of cycles between read and DQS pre */  in fsl_ddr_board_options()
28 	popts->cpo_override = 0xFF;  in fsl_ddr_board_options()
31 	popts->write_data_delay = 4;  in fsl_ddr_board_options()
33 	popts->clk_adjust = 4;  in fsl_ddr_board_options()
35 	popts->twot_en = 0;  in fsl_ddr_board_options()
38 	popts->half_strength_driver_enable = 1;  in fsl_ddr_board_options()
41 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
42 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
43 	popts->wrlvl_start = 0x6;  in fsl_ddr_board_options()
45 	/* Enable ZQ calibration */  in fsl_ddr_board_options()
46 	popts->zq_en = 1;  in fsl_ddr_board_options()
49 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;  in fsl_ddr_board_options()
64 	gd->ram_size = dram_size;  in dram_init()