Lines Matching +full:pre +full:- +full:calibration
1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
37 /* DN Resistor calibration code parameters */
86 /* Calibration digital logic parameters */
190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
204 * struct xpsgtr_phy - representation of a lane
224 * struct xpsgtr_dev - representation of a ZynMP GT device
278 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
283 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
298 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_read_phy()
299 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
307 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_write_phy()
308 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
316 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_clr_set_phy()
317 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
323 * xpsgtr_save_lane_regs - Saves registers on suspend
331 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev, in xpsgtr_save_lane_regs()
336 * xpsgtr_restore_lane_regs - Restores registers on resume
345 gtr_dev->saved_regs[i]); in xpsgtr_restore_lane_regs()
356 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_wait_pll_lock()
360 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); in xpsgtr_wait_pll_lock()
370 if (--timeout == 0) { in xpsgtr_wait_pll_lock()
371 ret = -ETIMEDOUT; in xpsgtr_wait_pll_lock()
378 if (ret == -ETIMEDOUT) in xpsgtr_wait_pll_lock()
379 dev_err(gtr_dev->dev, in xpsgtr_wait_pll_lock()
381 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
386 /* Configure PLL and spread-sprectrum clock. */
392 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
393 step_size = ssc->step_size; in xpsgtr_configure_pll()
395 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
396 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
399 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
400 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
403 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
404 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
422 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); in xpsgtr_configure_pll()
427 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); in xpsgtr_configure_pll()
439 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_lane_set_protocol()
440 u8 protocol = gtr_phy->protocol; in xpsgtr_lane_set_protocol()
442 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
470 /* DP-specific initialization. */
483 /* SATA-specific initialization. */
486 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sata()
490 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
493 /* SGMII-specific initialization. */
496 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sgmii()
497 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
498 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
507 /* Configure TX de-emphasis and margining for DP. */
508 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, in xpsgtr_phy_configure_dp() argument
524 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]); in xpsgtr_phy_configure_dp()
525 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]); in xpsgtr_phy_configure_dp()
538 * except when gtr_phy->skip_phy_init is false (this happens when FPD is in xpsgtr_phy_init_required()
541 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) in xpsgtr_phy_init_required()
549 * out of spec due to a issue in the calibration logic. This is the workaround
554 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_tx_term_fix()
568 * As a part of work around sequence for PMOS calibration fix, in xpsgtr_phy_tx_term_fix()
577 dev_dbg(gtr_dev->dev, "calibrating...\n"); in xpsgtr_phy_tx_term_fix()
585 if (!--timeout) { in xpsgtr_phy_tx_term_fix()
586 dev_err(gtr_dev->dev, "calibration time out\n"); in xpsgtr_phy_tx_term_fix()
587 return -ETIMEDOUT; in xpsgtr_phy_tx_term_fix()
593 dev_dbg(gtr_dev->dev, "calibration done\n"); in xpsgtr_phy_tx_term_fix()
618 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init()
621 mutex_lock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
624 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) in xpsgtr_phy_init()
631 if (gtr_dev->tx_term_fix) { in xpsgtr_phy_init()
636 gtr_dev->tx_term_fix = false; in xpsgtr_phy_init()
643 * Configure the PLL, the lane protocol, and perform protocol-specific in xpsgtr_phy_init()
649 switch (gtr_phy->protocol) { in xpsgtr_phy_init()
664 mutex_unlock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
671 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_exit()
673 gtr_phy->skip_phy_init = false; in xpsgtr_phy_exit()
676 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); in xpsgtr_phy_exit()
694 if (gtr_phy->protocol != ICM_PROTOCOL_DP || in xpsgtr_phy_power_on()
695 gtr_phy->type == XPSGTR_TYPE_DP_0) in xpsgtr_phy_power_on()
705 if (gtr_phy->protocol != ICM_PROTOCOL_DP) in xpsgtr_phy_configure()
708 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); in xpsgtr_phy_configure()
741 gtr_phy->protocol = ICM_PROTOCOL_SATA; in xpsgtr_set_lane_type()
752 gtr_phy->protocol = ICM_PROTOCOL_USB; in xpsgtr_set_lane_type()
763 gtr_phy->protocol = ICM_PROTOCOL_DP; in xpsgtr_set_lane_type()
776 gtr_phy->protocol = ICM_PROTOCOL_PCIE; in xpsgtr_set_lane_type()
789 gtr_phy->protocol = ICM_PROTOCOL_SGMII; in xpsgtr_set_lane_type()
793 return -EINVAL; in xpsgtr_set_lane_type()
797 return -EINVAL; in xpsgtr_set_lane_type()
799 gtr_phy->type = phy_types[phy_instance]; in xpsgtr_set_lane_type()
830 if (args->args_count != 4) { in xpsgtr_xlate()
832 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
839 phy_lane = args->args[0]; in xpsgtr_xlate()
840 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { in xpsgtr_xlate()
842 return ERR_PTR(-ENODEV); in xpsgtr_xlate()
845 gtr_phy = >r_dev->phys[phy_lane]; in xpsgtr_xlate()
846 phy_type = args->args[1]; in xpsgtr_xlate()
847 phy_instance = args->args[2]; in xpsgtr_xlate()
849 guard(mutex)(>r_phy->phy->mutex); in xpsgtr_xlate()
852 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); in xpsgtr_xlate()
856 refclk = args->args[3]; in xpsgtr_xlate()
857 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
858 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
860 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
863 gtr_phy->refclk = refclk; in xpsgtr_xlate()
870 if (icm_matrix[phy_lane][i] == gtr_phy->type) in xpsgtr_xlate()
871 return gtr_phy->phy; in xpsgtr_xlate()
874 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
886 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); in xpsgtr_runtime_suspend()
887 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); in xpsgtr_runtime_suspend()
907 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
911 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && in xpsgtr_runtime_resume()
912 icm_cfg1 == gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
918 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) in xpsgtr_runtime_resume()
919 gtr_dev->phys[i].skip_phy_init = skip_phy_init; in xpsgtr_runtime_resume()
934 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { in xpsgtr_get_ref_clocks()
941 clk = devm_clk_get_optional(gtr_dev->dev, name); in xpsgtr_get_ref_clocks()
943 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk), in xpsgtr_get_ref_clocks()
951 gtr_dev->clk[refclk] = clk; in xpsgtr_get_ref_clocks()
963 if (abs(rate - ssc_lookup[i].refclk_rate) < error) { in xpsgtr_get_ref_clocks()
964 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; in xpsgtr_get_ref_clocks()
970 dev_err(gtr_dev->dev, in xpsgtr_get_ref_clocks()
973 return -EINVAL; in xpsgtr_get_ref_clocks()
982 struct device_node *np = pdev->dev.of_node; in xpsgtr_probe()
988 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); in xpsgtr_probe()
990 return -ENOMEM; in xpsgtr_probe()
992 gtr_dev->dev = &pdev->dev; in xpsgtr_probe()
995 mutex_init(>r_dev->gtr_mutex); in xpsgtr_probe()
997 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) in xpsgtr_probe()
998 gtr_dev->tx_term_fix = in xpsgtr_probe()
999 of_property_read_bool(np, "xlnx,tx-termination-fix"); in xpsgtr_probe()
1002 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); in xpsgtr_probe()
1003 if (IS_ERR(gtr_dev->serdes)) in xpsgtr_probe()
1004 return PTR_ERR(gtr_dev->serdes); in xpsgtr_probe()
1006 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); in xpsgtr_probe()
1007 if (IS_ERR(gtr_dev->siou)) in xpsgtr_probe()
1008 return PTR_ERR(gtr_dev->siou); in xpsgtr_probe()
1015 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { in xpsgtr_probe()
1016 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; in xpsgtr_probe()
1019 gtr_phy->lane = port; in xpsgtr_probe()
1020 gtr_phy->dev = gtr_dev; in xpsgtr_probe()
1022 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); in xpsgtr_probe()
1024 dev_err(&pdev->dev, "failed to create PHY\n"); in xpsgtr_probe()
1028 gtr_phy->phy = phy; in xpsgtr_probe()
1033 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); in xpsgtr_probe()
1035 dev_err(&pdev->dev, "registering provider failed\n"); in xpsgtr_probe()
1039 pm_runtime_set_active(gtr_dev->dev); in xpsgtr_probe()
1040 pm_runtime_enable(gtr_dev->dev); in xpsgtr_probe()
1042 ret = pm_runtime_resume_and_get(gtr_dev->dev); in xpsgtr_probe()
1044 pm_runtime_disable(gtr_dev->dev); in xpsgtr_probe()
1048 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev, in xpsgtr_probe()
1051 if (!gtr_dev->saved_regs) in xpsgtr_probe()
1052 return -ENOMEM; in xpsgtr_probe()
1061 pm_runtime_disable(gtr_dev->dev); in xpsgtr_remove()
1062 pm_runtime_put_noidle(gtr_dev->dev); in xpsgtr_remove()
1063 pm_runtime_set_suspended(gtr_dev->dev); in xpsgtr_remove()
1069 { .compatible = "xlnx,zynqmp-psgtr", },
1070 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1079 .name = "xilinx-psgtr",