1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b7f2bbffSPrabhakar Kushwaha /* 3b7f2bbffSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 4b7f2bbffSPrabhakar Kushwaha */ 5b7f2bbffSPrabhakar Kushwaha 6b7f2bbffSPrabhakar Kushwaha #ifndef FSL_MMDC_H 7b7f2bbffSPrabhakar Kushwaha #define FSL_MMDC_H 8b7f2bbffSPrabhakar Kushwaha 9b9e745bbSShengzhou Liu /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ 10b9e745bbSShengzhou Liu #define MPWLGCR_HW_WL_EN (1 << 0) 11b7f2bbffSPrabhakar Kushwaha 12b7f2bbffSPrabhakar Kushwaha /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ 13b9e745bbSShengzhou Liu #define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) 14b7f2bbffSPrabhakar Kushwaha 15b7f2bbffSPrabhakar Kushwaha 16b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ 17b9e745bbSShengzhou Liu #define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) 18b7f2bbffSPrabhakar Kushwaha 19b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ 20b9e745bbSShengzhou Liu #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) 21b7f2bbffSPrabhakar Kushwaha 22b9e745bbSShengzhou Liu /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ 23b9e745bbSShengzhou Liu #define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 24b7f2bbffSPrabhakar Kushwaha 25b9e745bbSShengzhou Liu /* MMDC Core Refresh Control Register (MMDC_MDREF) */ 26b9e745bbSShengzhou Liu #define MDREF_START_REFRESH (1 << 0) 27b7f2bbffSPrabhakar Kushwaha 28b7f2bbffSPrabhakar Kushwaha /* MMDC Core Special Command Register (MDSCR) */ 29b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_MSB_MR_OP(x) (x << 24) 30b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) 31b9e745bbSShengzhou Liu #define MDSCR_DISABLE_CFG_REQ (0 << 15) 32b9e745bbSShengzhou Liu #define MDSCR_ENABLE_CON_REQ (1 << 15) 33b9e745bbSShengzhou Liu #define MDSCR_CON_ACK (1 << 14) 34b9e745bbSShengzhou Liu #define MDSCR_WL_EN (1 << 9) 35b9e745bbSShengzhou Liu #define CMD_NORMAL (0 << 4) 36b9e745bbSShengzhou Liu #define CMD_PRECHARGE (1 << 4) 37b9e745bbSShengzhou Liu #define CMD_AUTO_REFRESH (2 << 4) 38b9e745bbSShengzhou Liu #define CMD_LOAD_MODE_REG (3 << 4) 39b9e745bbSShengzhou Liu #define CMD_ZQ_CALIBRATION (4 << 4) 40b9e745bbSShengzhou Liu #define CMD_PRECHARGE_BANK_OPEN (5 << 4) 41b9e745bbSShengzhou Liu #define CMD_MRR (6 << 4) 42b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_0 0x0 43b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_1 0x1 44b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_2 0x2 45b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_3 0x3 46b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_4 0x4 47b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_5 0x5 48b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_6 0x6 49b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_7 0x7 50b7f2bbffSPrabhakar Kushwaha 51b9e745bbSShengzhou Liu /* MMDC Core Control Register (MDCTL) */ 52b9e745bbSShengzhou Liu #define MDCTL_SDE0 (1 << 31) 53b9e745bbSShengzhou Liu #define MDCTL_SDE1 (1 << 30) 54b9e745bbSShengzhou Liu 55b9e745bbSShengzhou Liu /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ 56b9e745bbSShengzhou Liu #define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) 57b9e745bbSShengzhou Liu 58b9e745bbSShengzhou Liu /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ 59b9e745bbSShengzhou Liu #define MMDC_MPMUR0_FRC_MSR (1 << 11) 60b9e745bbSShengzhou Liu 61b9e745bbSShengzhou Liu /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ 62b9e745bbSShengzhou Liu /* default 64 for a quarter cycle delay */ 63b9e745bbSShengzhou Liu #define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 64b9e745bbSShengzhou Liu 65b7f2bbffSPrabhakar Kushwaha /* MMDC Registers */ 66b9e745bbSShengzhou Liu struct mmdc_regs { 67b7f2bbffSPrabhakar Kushwaha u32 mdctl; 68b7f2bbffSPrabhakar Kushwaha u32 mdpdc; 69b7f2bbffSPrabhakar Kushwaha u32 mdotc; 70b7f2bbffSPrabhakar Kushwaha u32 mdcfg0; 71b7f2bbffSPrabhakar Kushwaha u32 mdcfg1; 72b7f2bbffSPrabhakar Kushwaha u32 mdcfg2; 73b7f2bbffSPrabhakar Kushwaha u32 mdmisc; 74b7f2bbffSPrabhakar Kushwaha u32 mdscr; 75b7f2bbffSPrabhakar Kushwaha u32 mdref; 76b7f2bbffSPrabhakar Kushwaha u32 res1[2]; 77b7f2bbffSPrabhakar Kushwaha u32 mdrwd; 78b7f2bbffSPrabhakar Kushwaha u32 mdor; 79b7f2bbffSPrabhakar Kushwaha u32 mdmrr; 80b7f2bbffSPrabhakar Kushwaha u32 mdcfg3lp; 81b7f2bbffSPrabhakar Kushwaha u32 mdmr4; 82b7f2bbffSPrabhakar Kushwaha u32 mdasp; 83b7f2bbffSPrabhakar Kushwaha u32 res2[239]; 84b7f2bbffSPrabhakar Kushwaha u32 maarcr; 85b7f2bbffSPrabhakar Kushwaha u32 mapsr; 86b7f2bbffSPrabhakar Kushwaha u32 maexidr0; 87b7f2bbffSPrabhakar Kushwaha u32 maexidr1; 88b7f2bbffSPrabhakar Kushwaha u32 madpcr0; 89b7f2bbffSPrabhakar Kushwaha u32 madpcr1; 90b7f2bbffSPrabhakar Kushwaha u32 madpsr0; 91b7f2bbffSPrabhakar Kushwaha u32 madpsr1; 92b7f2bbffSPrabhakar Kushwaha u32 madpsr2; 93b7f2bbffSPrabhakar Kushwaha u32 madpsr3; 94b7f2bbffSPrabhakar Kushwaha u32 madpsr4; 95b7f2bbffSPrabhakar Kushwaha u32 madpsr5; 96b7f2bbffSPrabhakar Kushwaha u32 masbs0; 97b7f2bbffSPrabhakar Kushwaha u32 masbs1; 98b7f2bbffSPrabhakar Kushwaha u32 res3[2]; 99b7f2bbffSPrabhakar Kushwaha u32 magenp; 100b7f2bbffSPrabhakar Kushwaha u32 res4[239]; 101b7f2bbffSPrabhakar Kushwaha u32 mpzqhwctrl; 102b7f2bbffSPrabhakar Kushwaha u32 mpzqswctrl; 103b7f2bbffSPrabhakar Kushwaha u32 mpwlgcr; 104b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl0; 105b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl1; 106b7f2bbffSPrabhakar Kushwaha u32 mpwldlst; 107b7f2bbffSPrabhakar Kushwaha u32 mpodtctrl; 108b7f2bbffSPrabhakar Kushwaha u32 mprddqby0dl; 109b7f2bbffSPrabhakar Kushwaha u32 mprddqby1dl; 110b7f2bbffSPrabhakar Kushwaha u32 mprddqby2dl; 111b7f2bbffSPrabhakar Kushwaha u32 mprddqby3dl; 112b9e745bbSShengzhou Liu u32 mpwrdqby0dl; 113b9e745bbSShengzhou Liu u32 mpwrdqby1dl; 114b9e745bbSShengzhou Liu u32 mpwrdqby2dl; 115b9e745bbSShengzhou Liu u32 mpwrdqby3dl; 116b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl0; 117b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl1; 118b7f2bbffSPrabhakar Kushwaha u32 mpdgdlst0; 119b7f2bbffSPrabhakar Kushwaha u32 mprddlctl; 120b7f2bbffSPrabhakar Kushwaha u32 mprddlst; 121b7f2bbffSPrabhakar Kushwaha u32 mpwrdlctl; 122b7f2bbffSPrabhakar Kushwaha u32 mpwrdlst; 123b7f2bbffSPrabhakar Kushwaha u32 mpsdctrl; 124b7f2bbffSPrabhakar Kushwaha u32 mpzqlp2ctl; 125b7f2bbffSPrabhakar Kushwaha u32 mprddlhwctl; 126b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwctl; 127b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst0; 128b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst1; 129b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst0; 130b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst1; 131b7f2bbffSPrabhakar Kushwaha u32 mpwlhwerr; 132b7f2bbffSPrabhakar Kushwaha u32 mpdghwst0; 133b7f2bbffSPrabhakar Kushwaha u32 mpdghwst1; 134b7f2bbffSPrabhakar Kushwaha u32 mpdghwst2; 135b7f2bbffSPrabhakar Kushwaha u32 mpdghwst3; 136b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr1; 137b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr2; 138b7f2bbffSPrabhakar Kushwaha u32 mpswdar0; 139b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr0; 140b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr1; 141b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr2; 142b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr3; 143b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr4; 144b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr5; 145b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr6; 146b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr7; 147b7f2bbffSPrabhakar Kushwaha u32 mpmur0; 148b7f2bbffSPrabhakar Kushwaha u32 mpwrcadl; 149b7f2bbffSPrabhakar Kushwaha u32 mpdccr; 150b7f2bbffSPrabhakar Kushwaha }; 151b7f2bbffSPrabhakar Kushwaha 1521fdcc8dfSYork Sun struct fsl_mmdc_info { 1531fdcc8dfSYork Sun u32 mdctl; 1541fdcc8dfSYork Sun u32 mdpdc; 1551fdcc8dfSYork Sun u32 mdotc; 1561fdcc8dfSYork Sun u32 mdcfg0; 1571fdcc8dfSYork Sun u32 mdcfg1; 1581fdcc8dfSYork Sun u32 mdcfg2; 1591fdcc8dfSYork Sun u32 mdmisc; 1601fdcc8dfSYork Sun u32 mdref; 1611fdcc8dfSYork Sun u32 mdrwd; 1621fdcc8dfSYork Sun u32 mdor; 1631fdcc8dfSYork Sun u32 mdasp; 1641fdcc8dfSYork Sun u32 mpodtctrl; 1651fdcc8dfSYork Sun u32 mpzqhwctrl; 1661fdcc8dfSYork Sun u32 mprddlctl; 1671fdcc8dfSYork Sun }; 168b9e745bbSShengzhou Liu 1691fdcc8dfSYork Sun void mmdc_init(const struct fsl_mmdc_info *); 170b9e745bbSShengzhou Liu 171b7f2bbffSPrabhakar Kushwaha #endif /* FSL_MMDC_H */ 172