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/openbmc/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-pll.c57 * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
61 * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
63 * all the devices consuming those PLLs, they will be marked as critical too.
81 struct ccu_pll *plls[CCU_PLL_NUM]; member
93 return data->plls[idx]; in ccu_pll_find_desc()
156 /* Defer non-basic PLLs allocation for the probe stage */ in ccu_pll_clk_register()
158 if (!data->plls[idx]) in ccu_pll_clk_register()
159 data->plls[idx] = ERR_PTR(-EPROBE_DEFER); in ccu_pll_clk_register()
173 data->plls[idx] = ccu_pll_hw_register(&init); in ccu_pll_clk_register()
[all …]
H A DKconfig11 in them are fed with clocks generated by a hierarchy of PLLs,
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
23 System Controller. These are five PLLs placed at the root of the
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
23 2) PLLs clocks generators (PLLs) - described in this binding file.
31 | +-|PLLs|------|- DDR controller
47 output is primarily connected to a set of CCU PLLs. There are five PLLs
51 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53 the PLL configuration procedure. The PLLs work as depicted on the next
77 The PLLs CLKOUT is then either directly connected with the corresponding
H A Dbaikal,bt1-ccu-div.yaml19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 in general can provide any frequency supported by the CCU PLLs).
25 2) PLLs clocks generators (PLLs).
34 | +-|PLLs|------|- DDR controller
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8135-apmixedsys.c37 static const struct mtk_pll_data plls[] = { variable
60 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8135_apmixed_probe()
71 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8135_apmixed_probe()
84 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8135_apmixed_remove()
H A Dclk-mt7622-apmixedsys.c58 static const struct mtk_pll_data plls[] = { variable
99 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt7622_apmixed_probe()
117 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt7622_apmixed_probe()
129 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt7622_apmixed_remove()
H A Dclk-mt8186-apmixedsys.c46 static const struct mtk_pll_data plls[] = { variable
154 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), in clk_mt8186_apmixed_probe()
168 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8186_apmixed_probe()
181 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8186_apmixed_remove()
H A Dclk-mt8188-apmixedsys.c60 static const struct mtk_pll_data plls[] = { variable
109 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8188_apmixed_probe()
129 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8188_apmixed_probe()
142 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8188_apmixed_remove()
H A Dclk-mt2712-apmixedsys.c79 static const struct mtk_pll_data plls[] = { variable
122 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt2712_apmixed_probe()
135 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt2712_apmixed_probe()
147 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt2712_apmixed_remove()
H A Dclk-mt8192-apmixedsys.c72 static const struct mtk_pll_data plls[] = { variable
165 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), in clk_mt8192_apmixed_probe()
184 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8192_apmixed_probe()
198 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8192_apmixed_remove()
H A Dclk-mt6795-apmixedsys.c46 static const struct mtk_pll_data plls[] = { variable
155 ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), in clk_mt6795_apmixed_probe()
183 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt6795_apmixed_probe()
197 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt6795_apmixed_remove()
H A Dclk-mt8516-apmixedsys.c59 static const struct mtk_pll_data plls[] = { variable
90 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8516_apmixed_probe()
101 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8516_apmixed_probe()
H A Dclk-mt8173-apmixedsys.c60 static const struct mtk_pll_data plls[] = { variable
160 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), in clk_mt8173_apmixed_probe()
187 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8173_apmixed_probe()
202 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8173_apmixed_remove()
H A Dclk-mt8167-apmixedsys.c58 static const struct mtk_pll_data plls[] = { variable
108 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8167_apmixed_probe()
126 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8167_apmixed_probe()
H A Dclk-mt8183-apmixedsys.c33 * apmixed_appll26m is the toppest clock gate of all PLLs.
110 static const struct mtk_pll_data plls[] = { variable
158 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8183_apmixed_probe()
176 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8183_apmixed_probe()
H A Dclk-mt7986-apmixed.c42 static const struct mtk_pll_data plls[] = { variable
73 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); in clk_mt7986_apmixed_probe()
77 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt7986_apmixed_probe()
H A Dclk-mt8195-apmixedsys.c61 static const struct mtk_pll_data plls[] = { variable
184 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), in clk_mt8195_apmixed_probe()
205 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8195_apmixed_probe()
219 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, in clk_mt8195_apmixed_remove()
H A Dclk-mt7981-apmixed.c44 static const struct mtk_pll_data plls[] = { variable
75 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); in clk_mt7981_apmixed_probe()
79 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt7981_apmixed_probe()
H A Dclk-mt8365-apmixedsys.c82 static const struct mtk_pll_data plls[] = { variable
136 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8365_apmixed_probe()
147 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8365_apmixed_probe()
H A Dclk-pll.h54 * MediaTek PLLs are configured through their pcw value. The pcw value describes
74 const struct mtk_pll_data *plls, int num_plls,
76 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
/openbmc/linux/drivers/clk/bcm/
H A Dclk-iproc.h36 * Some PLLs require the PLL SW override bit to be set before changes can be
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
48 * Some PLLs have separate registers for Status and Control. Identify this to
54 * Some PLLs have an additional divide by 2 in master clock calculation;
61 * Some PLLs provide a look up table for the leaf clock frequencies and
69 * Some PLLs have an active low reset
181 * Main clock control parameters for clocks derived from the PLLs
/openbmc/qemu/hw/misc/
H A Dbcm2835_cprman.c11 * - the PLLs
15 * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
24 * dividers (and multipliers in case of the PLLs), and can be disabled (in this
446 r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; in get_cm_lock()
479 pll_update_all_channels(s, &s->plls[i]); in update_pll_and_channels_from_cm()
546 pll_update(&s->plls[CPRMAN_PLLA]); in cprman_write()
550 pll_update(&s->plls[CPRMAN_PLLC]); in cprman_write()
554 pll_update(&s->plls[CPRMAN_PLLD]); in cprman_write()
558 pll_update(&s->plls[CPRMAN_PLLH]); in cprman_write()
562 pll_update(&s->plls[CPRMAN_PLLB]); in cprman_write()
[all …]
H A Dstm32l4x5_rcc.c426 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val); in rcc_update_cr_register()
435 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val); in rcc_update_cr_register()
448 pll_set_enable(&s->plls[RCC_PLL_PLL], val); in rcc_update_cr_register()
737 * The 3 PLLs share the same register layout
766 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
769 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
776 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, in rcc_update_pllsaixcfgr()
781 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val); in rcc_update_pllsaixcfgr()
785 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, in rcc_update_pllsaixcfgr()
790 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val); in rcc_update_pllsaixcfgr()
[all …]
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs52 CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs
54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
56 value as 5 not 4, to iterate over all PLLs while coding
/openbmc/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()

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