1b7d950b9SSerge Semin# SPDX-License-Identifier: GPL-2.0-only 2b7d950b9SSerge Seminconfig CLK_BAIKAL_T1 3b7d950b9SSerge Semin bool "Baikal-T1 Clocks Control Unit interface" 4b7d950b9SSerge Semin depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST 5b7d950b9SSerge Semin default MIPS_BAIKAL_T1 6b7d950b9SSerge Semin help 7b7d950b9SSerge Semin Clocks Control Unit is the core of Baikal-T1 SoC System Controller 8b7d950b9SSerge Semin responsible for the chip subsystems clocking and resetting. It 9b7d950b9SSerge Semin consists of multiple global clock domains, which can be reset by 10b7d950b9SSerge Semin means of the CCU control registers. These domains and devices placed 11b7d950b9SSerge Semin in them are fed with clocks generated by a hierarchy of PLLs, 12b7d950b9SSerge Semin configurable and fixed clock dividers. Enable this option to be able 13b7d950b9SSerge Semin to select Baikal-T1 CCU PLLs and Dividers drivers. 14b7d950b9SSerge Semin 15b7d950b9SSerge Seminif CLK_BAIKAL_T1 16b7d950b9SSerge Semin 17b7d950b9SSerge Seminconfig CLK_BT1_CCU_PLL 18b7d950b9SSerge Semin bool "Baikal-T1 CCU PLLs support" 19b7d950b9SSerge Semin select MFD_SYSCON 20b7d950b9SSerge Semin default MIPS_BAIKAL_T1 21b7d950b9SSerge Semin help 22b7d950b9SSerge Semin Enable this to support the PLLs embedded into the Baikal-T1 SoC 23b7d950b9SSerge Semin System Controller. These are five PLLs placed at the root of the 24b7d950b9SSerge Semin clocks hierarchy, right after an external reference oscillator 25b7d950b9SSerge Semin (normally of 25MHz). They are used to generate high frequency 26b7d950b9SSerge Semin signals, which are either directly wired to the consumers (like 27b7d950b9SSerge Semin CPUs, DDR, etc.) or passed over the clock dividers to be only 28b7d950b9SSerge Semin then used as an individual reference clock of a target device. 29b7d950b9SSerge Semin 30353afa3aSSerge Seminconfig CLK_BT1_CCU_DIV 31353afa3aSSerge Semin bool "Baikal-T1 CCU Dividers support" 32353afa3aSSerge Semin select MFD_SYSCON 33353afa3aSSerge Semin default MIPS_BAIKAL_T1 34353afa3aSSerge Semin help 35353afa3aSSerge Semin Enable this to support the CCU dividers used to distribute clocks 36353afa3aSSerge Semin between AXI-bus and system devices coming from CCU PLLs of Baikal-T1 37353afa3aSSerge Semin SoC. CCU dividers can be either configurable or with fixed divider, 38353afa3aSSerge Semin either gateable or ungateable. Some of the CCU dividers can be as well 39353afa3aSSerge Semin used to reset the domains they're supplying clock to. 40353afa3aSSerge Semin 41*70fa8954SSerge Seminconfig CLK_BT1_CCU_RST 42*70fa8954SSerge Semin bool "Baikal-T1 CCU Resets support" 43*70fa8954SSerge Semin select RESET_CONTROLLER 44*70fa8954SSerge Semin select MFD_SYSCON 45*70fa8954SSerge Semin default MIPS_BAIKAL_T1 46*70fa8954SSerge Semin help 47*70fa8954SSerge Semin Enable this to support the CCU reset blocks responsible for the 48*70fa8954SSerge Semin AXI-bus and some subsystems reset. These are mainly the 49*70fa8954SSerge Semin self-deasserted reset controls but there are several lines which 50*70fa8954SSerge Semin can be directly asserted/de-asserted (PCIe and DDR sub-domains). 51*70fa8954SSerge Semin 52b7d950b9SSerge Seminendif 53