139691fb6SChen-Yu Tsai /* SPDX-License-Identifier: GPL-2.0-only */
239691fb6SChen-Yu Tsai /*
339691fb6SChen-Yu Tsai * Copyright (c) 2014 MediaTek Inc.
439691fb6SChen-Yu Tsai * Author: James Liao <jamesjj.liao@mediatek.com>
539691fb6SChen-Yu Tsai */
639691fb6SChen-Yu Tsai
739691fb6SChen-Yu Tsai #ifndef __DRV_CLK_MTK_PLL_H
839691fb6SChen-Yu Tsai #define __DRV_CLK_MTK_PLL_H
939691fb6SChen-Yu Tsai
10*029c936aSJohnson Wang #include <linux/clk-provider.h>
1139691fb6SChen-Yu Tsai #include <linux/types.h>
1239691fb6SChen-Yu Tsai
1339691fb6SChen-Yu Tsai struct clk_ops;
14609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data;
1539691fb6SChen-Yu Tsai struct device_node;
1639691fb6SChen-Yu Tsai
1739691fb6SChen-Yu Tsai struct mtk_pll_div_table {
1839691fb6SChen-Yu Tsai u32 div;
1939691fb6SChen-Yu Tsai unsigned long freq;
2039691fb6SChen-Yu Tsai };
2139691fb6SChen-Yu Tsai
2239691fb6SChen-Yu Tsai #define HAVE_RST_BAR BIT(0)
2339691fb6SChen-Yu Tsai #define PLL_AO BIT(1)
24*029c936aSJohnson Wang #define POSTDIV_MASK GENMASK(2, 0)
2539691fb6SChen-Yu Tsai
2639691fb6SChen-Yu Tsai struct mtk_pll_data {
2739691fb6SChen-Yu Tsai int id;
2839691fb6SChen-Yu Tsai const char *name;
2939691fb6SChen-Yu Tsai u32 reg;
3039691fb6SChen-Yu Tsai u32 pwr_reg;
3139691fb6SChen-Yu Tsai u32 en_mask;
3239691fb6SChen-Yu Tsai u32 pd_reg;
3339691fb6SChen-Yu Tsai u32 tuner_reg;
3439691fb6SChen-Yu Tsai u32 tuner_en_reg;
3539691fb6SChen-Yu Tsai u8 tuner_en_bit;
3639691fb6SChen-Yu Tsai int pd_shift;
3739691fb6SChen-Yu Tsai unsigned int flags;
3839691fb6SChen-Yu Tsai const struct clk_ops *ops;
3939691fb6SChen-Yu Tsai u32 rst_bar_mask;
4039691fb6SChen-Yu Tsai unsigned long fmin;
4139691fb6SChen-Yu Tsai unsigned long fmax;
4239691fb6SChen-Yu Tsai int pcwbits;
4339691fb6SChen-Yu Tsai int pcwibits;
4439691fb6SChen-Yu Tsai u32 pcw_reg;
4539691fb6SChen-Yu Tsai int pcw_shift;
4639691fb6SChen-Yu Tsai u32 pcw_chg_reg;
4739691fb6SChen-Yu Tsai const struct mtk_pll_div_table *div_table;
4839691fb6SChen-Yu Tsai const char *parent_name;
4939691fb6SChen-Yu Tsai u32 en_reg;
5039691fb6SChen-Yu Tsai u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
5139691fb6SChen-Yu Tsai };
5239691fb6SChen-Yu Tsai
53*029c936aSJohnson Wang /*
54*029c936aSJohnson Wang * MediaTek PLLs are configured through their pcw value. The pcw value describes
55*029c936aSJohnson Wang * a divider in the PLL feedback loop which consists of 7 bits for the integer
56*029c936aSJohnson Wang * part and the remaining bits (if present) for the fractional part. Also they
57*029c936aSJohnson Wang * have a 3 bit power-of-two post divider.
58*029c936aSJohnson Wang */
59*029c936aSJohnson Wang
60*029c936aSJohnson Wang struct mtk_clk_pll {
61*029c936aSJohnson Wang struct clk_hw hw;
62*029c936aSJohnson Wang void __iomem *base_addr;
63*029c936aSJohnson Wang void __iomem *pd_addr;
64*029c936aSJohnson Wang void __iomem *pwr_addr;
65*029c936aSJohnson Wang void __iomem *tuner_addr;
66*029c936aSJohnson Wang void __iomem *tuner_en_addr;
67*029c936aSJohnson Wang void __iomem *pcw_addr;
68*029c936aSJohnson Wang void __iomem *pcw_chg_addr;
69*029c936aSJohnson Wang void __iomem *en_addr;
70*029c936aSJohnson Wang const struct mtk_pll_data *data;
71*029c936aSJohnson Wang };
72*029c936aSJohnson Wang
736ae34f2bSChen-Yu Tsai int mtk_clk_register_plls(struct device_node *node,
7439691fb6SChen-Yu Tsai const struct mtk_pll_data *plls, int num_plls,
75609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data);
766dd19906SChen-Yu Tsai void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
77609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data);
7839691fb6SChen-Yu Tsai
79*029c936aSJohnson Wang extern const struct clk_ops mtk_pll_ops;
80*029c936aSJohnson Wang
to_mtk_clk_pll(struct clk_hw * hw)81*029c936aSJohnson Wang static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
82*029c936aSJohnson Wang {
83*029c936aSJohnson Wang return container_of(hw, struct mtk_clk_pll, hw);
84*029c936aSJohnson Wang }
85*029c936aSJohnson Wang
86*029c936aSJohnson Wang int mtk_pll_is_prepared(struct clk_hw *hw);
87*029c936aSJohnson Wang
88*029c936aSJohnson Wang int mtk_pll_prepare(struct clk_hw *hw);
89*029c936aSJohnson Wang
90*029c936aSJohnson Wang void mtk_pll_unprepare(struct clk_hw *hw);
91*029c936aSJohnson Wang
92*029c936aSJohnson Wang unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
93*029c936aSJohnson Wang
94*029c936aSJohnson Wang void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
95*029c936aSJohnson Wang u32 freq, u32 fin);
96*029c936aSJohnson Wang int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
97*029c936aSJohnson Wang unsigned long parent_rate);
98*029c936aSJohnson Wang long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
99*029c936aSJohnson Wang unsigned long *prate);
100*029c936aSJohnson Wang
101*029c936aSJohnson Wang struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
102*029c936aSJohnson Wang const struct mtk_pll_data *data,
103*029c936aSJohnson Wang void __iomem *base,
104*029c936aSJohnson Wang const struct clk_ops *pll_ops);
105*029c936aSJohnson Wang struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
106*029c936aSJohnson Wang void __iomem *base);
107*029c936aSJohnson Wang void mtk_clk_unregister_pll(struct clk_hw *hw);
108*029c936aSJohnson Wang
109*029c936aSJohnson Wang __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
110*029c936aSJohnson Wang const struct mtk_pll_data *data);
111*029c936aSJohnson Wang
11239691fb6SChen-Yu Tsai #endif /* __DRV_CLK_MTK_PLL_H */
113