426     pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val);  in rcc_update_cr_register()
435     pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val);  in rcc_update_cr_register()
448         pll_set_enable(&s->plls[RCC_PLL_PLL], val);  in rcc_update_cr_register()
737  * The 3 PLLs share the same register layout
766         pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,  in rcc_update_pllsaixcfgr()
769         pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,  in rcc_update_pllsaixcfgr()
776     pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R,  in rcc_update_pllsaixcfgr()
781     pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val);  in rcc_update_pllsaixcfgr()
785     pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q,  in rcc_update_pllsaixcfgr()
790     pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val);  in rcc_update_pllsaixcfgr()
794     pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, val);  in rcc_update_pllsaixcfgr()
798     pll_set_vco_multiplier(&s->plls[pll_id], val);  in rcc_update_pllsaixcfgr()
1268                                 &s->plls[i], TYPE_RCC_PLL);  in stm32l4x5_rcc_init()
1269         set_pll_init_info(&s->plls[i], i);  in stm32l4x5_rcc_init()
1307             s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK],  in connect_mux_sources()
1309             s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK],  in connect_mux_sources()
1311             s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK],  in connect_mux_sources()
1313             s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK],  in connect_mux_sources()
1315             s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK],  in connect_mux_sources()
1317             s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK],  in connect_mux_sources()
1319             s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLADC1CLK],  in connect_mux_sources()
1321             s->plls[RCC_PLL_PLLSAI2] .channels[RCC_PLLSAI2_CHANNEL_PLLADC2CLK],  in connect_mux_sources()
1400         RccPllState *pll = &s->plls[i];  in stm32l4x5_rcc_realize()