1aec6adc5SSerge Semin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2aec6adc5SSerge Semin# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 3aec6adc5SSerge Semin%YAML 1.2 4aec6adc5SSerge Semin--- 5aec6adc5SSerge Semin$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml# 6aec6adc5SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 7aec6adc5SSerge Semin 8aec6adc5SSerge Semintitle: Baikal-T1 Clock Control Unit PLL 9aec6adc5SSerge Semin 10aec6adc5SSerge Seminmaintainers: 11aec6adc5SSerge Semin - Serge Semin <fancer.lancer@gmail.com> 12aec6adc5SSerge Semin 13aec6adc5SSerge Semindescription: | 14aec6adc5SSerge Semin Clocks Control Unit is the core of Baikal-T1 SoC System Controller 15aec6adc5SSerge Semin responsible for the chip subsystems clocking and resetting. The CCU is 16aec6adc5SSerge Semin connected with an external fixed rate oscillator, which signal is transformed 17aec6adc5SSerge Semin into clocks of various frequencies and then propagated to either individual 18aec6adc5SSerge Semin IP-blocks or to groups of blocks (clock domains). The transformation is done 19aec6adc5SSerge Semin by means of PLLs and gateable/non-gateable dividers embedded into the CCU. 20aec6adc5SSerge Semin It's logically divided into the next components: 21aec6adc5SSerge Semin 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but 22aec6adc5SSerge Semin in general can provide any frequency supported by the CCU PLLs). 23aec6adc5SSerge Semin 2) PLLs clocks generators (PLLs) - described in this binding file. 24aec6adc5SSerge Semin 3) AXI-bus clock dividers (AXI). 25aec6adc5SSerge Semin 4) System devices reference clock dividers (SYS). 26aec6adc5SSerge Semin which are connected with each other as shown on the next figure: 27aec6adc5SSerge Semin 28aec6adc5SSerge Semin +---------------+ 29aec6adc5SSerge Semin | Baikal-T1 CCU | 30aec6adc5SSerge Semin | +----+------|- MIPS P5600 cores 31aec6adc5SSerge Semin | +-|PLLs|------|- DDR controller 32aec6adc5SSerge Semin | | +----+ | 33aec6adc5SSerge Semin +----+ | | | | | 34aec6adc5SSerge Semin |XTAL|--|-+ | | +---+-| 35aec6adc5SSerge Semin +----+ | | | +-|AXI|-|- AXI-bus 36aec6adc5SSerge Semin | | | +---+-| 37aec6adc5SSerge Semin | | | | 38aec6adc5SSerge Semin | | +----+---+-|- APB-bus 39aec6adc5SSerge Semin | +-------|SYS|-|- Low-speed Devices 40aec6adc5SSerge Semin | +---+-|- High-speed Devices 41aec6adc5SSerge Semin +---------------+ 42aec6adc5SSerge Semin 43aec6adc5SSerge Semin Each CCU sub-block is represented as a separate dts-node and has an 44aec6adc5SSerge Semin individual driver to be bound with. 45aec6adc5SSerge Semin 46aec6adc5SSerge Semin In order to create signals of wide range frequencies the external oscillator 47aec6adc5SSerge Semin output is primarily connected to a set of CCU PLLs. There are five PLLs 48aec6adc5SSerge Semin to create a clock for the MIPS P5600 cores, the embedded DDR controller, 49aec6adc5SSerge Semin SATA, Ethernet and PCIe domains. The last three domains though named by the 50aec6adc5SSerge Semin biggest system interfaces in fact include nearly all of the rest SoC 51aec6adc5SSerge Semin peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core 52aec6adc5SSerge Semin with an interface wrapper (so called safe PLL' clocks switcher) to simplify 53aec6adc5SSerge Semin the PLL configuration procedure. The PLLs work as depicted on the next 54aec6adc5SSerge Semin diagram: 55aec6adc5SSerge Semin 56aec6adc5SSerge Semin +--------------------------+ 57aec6adc5SSerge Semin | | 58aec6adc5SSerge Semin +-->+---+ +---+ +---+ | +---+ 0|\ 59aec6adc5SSerge Semin CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| | 60aec6adc5SSerge Semin +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT 61aec6adc5SSerge Semin CLKOD---------C----------------+ 1| | 62aec6adc5SSerge Semin +--------C--------------------------->|/ 63aec6adc5SSerge Semin | | ^ 64aec6adc5SSerge Semin Rclk-+->+---+ | | 65aec6adc5SSerge Semin CLKR--->|/NR|-+ | 66aec6adc5SSerge Semin +---+ | 67aec6adc5SSerge Semin BYPASS--------------------------------------+ 68aec6adc5SSerge Semin BWADJ---> 69aec6adc5SSerge Semin 70aec6adc5SSerge Semin where Rclk is the reference clock coming from XTAL, NR - reference clock 71aec6adc5SSerge Semin divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT - 72aec6adc5SSerge Semin output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment 73aec6adc5SSerge Semin the binding supports the PLL dividers configuration in accordance with a 74aec6adc5SSerge Semin requested rate, while bypassing and bandwidth adjustment settings can be 75aec6adc5SSerge Semin added in future if it gets to be necessary. 76aec6adc5SSerge Semin 77aec6adc5SSerge Semin The PLLs CLKOUT is then either directly connected with the corresponding 78aec6adc5SSerge Semin clocks consumer (like P5600 cores or DDR controller) or passed over a CCU 79aec6adc5SSerge Semin divider to create a signal required for the clock domain. 80aec6adc5SSerge Semin 81aec6adc5SSerge Semin The CCU PLL dts-node uses the common clock bindings with no custom 82aec6adc5SSerge Semin parameters. The list of exported clocks can be found in 83aec6adc5SSerge Semin 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the 84aec6adc5SSerge Semin Baikal-T1 SoC System Controller its DT node is supposed to be a child of 85aec6adc5SSerge Semin later one. 86aec6adc5SSerge Semin 87aec6adc5SSerge Seminproperties: 88aec6adc5SSerge Semin compatible: 89aec6adc5SSerge Semin const: baikal,bt1-ccu-pll 90aec6adc5SSerge Semin 91aec6adc5SSerge Semin reg: 92aec6adc5SSerge Semin maxItems: 1 93aec6adc5SSerge Semin 94aec6adc5SSerge Semin "#clock-cells": 95aec6adc5SSerge Semin const: 1 96aec6adc5SSerge Semin 97aec6adc5SSerge Semin clocks: 98aec6adc5SSerge Semin description: External reference clock 99aec6adc5SSerge Semin maxItems: 1 100aec6adc5SSerge Semin 101aec6adc5SSerge Semin clock-names: 102aec6adc5SSerge Semin const: ref_clk 103aec6adc5SSerge Semin 1044828556dSRob HerringadditionalProperties: false 105aec6adc5SSerge Semin 106aec6adc5SSerge Seminrequired: 107aec6adc5SSerge Semin - compatible 108aec6adc5SSerge Semin - "#clock-cells" 109aec6adc5SSerge Semin - clocks 110aec6adc5SSerge Semin - clock-names 111aec6adc5SSerge Semin 112aec6adc5SSerge Seminexamples: 113aec6adc5SSerge Semin # Clock Control Unit PLL node: 114aec6adc5SSerge Semin - | 115aec6adc5SSerge Semin clock-controller@1f04d000 { 116aec6adc5SSerge Semin compatible = "baikal,bt1-ccu-pll"; 117aec6adc5SSerge Semin reg = <0x1f04d000 0x028>; 118aec6adc5SSerge Semin #clock-cells = <1>; 119aec6adc5SSerge Semin 120aec6adc5SSerge Semin clocks = <&clk25m>; 121aec6adc5SSerge Semin clock-names = "ref_clk"; 122aec6adc5SSerge Semin }; 123aec6adc5SSerge Semin # Required external oscillator: 124aec6adc5SSerge Semin - | 125aec6adc5SSerge Semin clk25m: clock-oscillator-25m { 126aec6adc5SSerge Semin compatible = "fixed-clock"; 127aec6adc5SSerge Semin #clock-cells = <0>; 128aec6adc5SSerge Semin clock-frequency = <25000000>; 129aec6adc5SSerge Semin clock-output-names = "clk25m"; 130aec6adc5SSerge Semin }; 131aec6adc5SSerge Semin... 132