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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt57 - pex
64 - pex
85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
[all …]
H A Dnvidia,tegra194-pcie-ep.yaml162 vddio-pex-ctl-supply:
200 - vddio-pex-ctl-supply
246 vddio-pex-ctl-supply = <&vdd_1v8ao>;
302 vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml87 csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
88 pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
89 hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
95 csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
96 pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
99 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
100 pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
H A Dnvidia,tegra20-pmc.yaml291 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
297 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
323 All of the listed Tegra210 pads except pex-cntrl support power
326 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.c31 /* configuration for PEX only */ in hws_pex_config()
39 /* for PEX by4 - relevant for the first port only */ in hws_pex_config()
58 /* for PEX by4 - relevant for the first port only */ in hws_pex_config()
99 /* Configuration for PEX only */ in hws_pex_config()
107 /* for PEX by4 - relevant for the first port only */ in hws_pex_config()
197 /* Update pex DEVICE ID */ in hws_pex_config()
202 /* configuration for PEX only */ in hws_pex_config()
210 /* for PEX by4 - relevant for the first port only */ in hws_pex_config()
222 DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4); in hws_pex_config()
267 * This function performs a 32 bit read from PEX configuration space.
[all …]
H A Dhigh_speed_env_spec.c47 { 1, 1, 1, 1 }, /* PEX */
89 /* Selector mapping for PEX by 4 confiuration */
406 * PEX and USB3
409 /* PEX and USB3 - power up seq for Serdes Rev 1.2 */
412 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
425 /* PEX and USB3 - power up seq for Serdes Rev 2.1 */
428 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
442 /* PEX and USB3 - speed config seq */
445 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
487 /* PEX and USB3 - TX config seq */
[all …]
H A Dhigh_speed_env_spec.h76 SERDES_DEFAULT_MODE, /* not pex */
169 /* The different sequence types for PEX and USB3 */
171 PEX, enumerator
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c131 /* SERDES module (only PEX model is supported now) */ in board_modules_scan()
234 * configuration pulse for the PEX link detection might lead to
371 info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */ in serdes_phy_config()
395 /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */ in serdes_phy_config()
396 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n"); in serdes_phy_config()
543 DEBUG_INIT_FULL_S(" - PEX unit "); in serdes_phy_config()
563 * [PEX-Only] Set bit[12]: The analog part latches idle in serdes_phy_config()
630 /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */ in serdes_phy_config()
631 DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n"); in serdes_phy_config()
647 DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n"); in serdes_phy_config()
[all …]
H A Dhigh_speed_env_spec.c17 /* PEX: Change of Slew Rate port0 */
21 /* PEX: Change PLL BW port0 */
67 0x0030, serdes_change_m_phy}, /* PEX module */
74 0x0030, serdes_change_m_phy} /* PEX module - Z1A */
81 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
84 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
87 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
90 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
93 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
96 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
[all …]
H A Dboard_env_spec.h121 /* This define describes the maximum number of supported PEX Interfaces */
164 #define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) argument
165 #define SCR_PEX_ENA_MASK(pex) (1 << pex) argument
170 #define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) argument
171 #define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) argument
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dpcie.c56 pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; in mpc83xx_pcie_remap_cfg() local
57 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_remap_cfg()
180 pex83xx_t *pex = &immr->pciexp[bus]; in mpc83xx_pcie_init_bus() local
190 /* Enable pex csb bridge inbound & outbound transactions */ in mpc83xx_pcie_init_bus()
191 out_le32(&pex->bridge.pex_csb_ctrl, in mpc83xx_pcie_init_bus()
192 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | in mpc83xx_pcie_init_bus()
196 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | in mpc83xx_pcie_init_bus()
200 out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_init_bus()
213 out_win = &pex->bridge.pex_outbound_win[i + 1]; in mpc83xx_pcie_init_bus()
225 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); in mpc83xx_pcie_init_bus()
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h128 uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
129 uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
131 uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
133 uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
134 uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
135 uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
136 uint pm_command; /* 0x802c - PEX PM Command register */
138 uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
139 uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
140 uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml108 avddio-pex-supply:
111 dvddio-pex-supply:
149 - avddio-pex-supply
150 - dvddio-pex-supply
192 avddio-pex-supply = <&vdd_1v05_run>;
193 dvddio-pex-supply = <&vdd_1v05_run>;
H A Dnvidia,tegra210-xusb.yaml111 dvddio-pex-supply:
114 hvddio-pex-supply:
180 dvddio-pex-supply = <&vdd_pex_1v05>;
181 hvddio-pex-supply = <&vdd_1v8>;
/openbmc/u-boot/Documentation/devicetree/bindings/misc/
H A Dfsl,mpc83xx-serdes.txt11 "sata", "pex", "pex-x2", "sgmii"
21 proto = "pex";
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dbsc9132qds.c53 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ in board_config_serdes_mux()
67 /* PEX(1) PEX(2) SGMII1 CPRI 1 */ in board_config_serdes_mux()
81 /* PEX(1) PEX(2) SGMII1 SGMII2 */ in board_config_serdes_mux()
87 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ in board_config_serdes_mux()
101 /* PEX(1) SGMII2 SGMII1 CPRI 1 */ in board_config_serdes_mux()
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-trimslice.dts36 avdd-pex-supply = <&pci_vdd_reg>;
37 vdd-pex-supply = <&pci_vdd_reg>;
38 avdd-pex-pll-supply = <&pci_vdd_reg>;
40 vddio-pex-clk-supply = <&pci_clk_reg>;
H A Dtegra124-jetson-tk1.dts35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
40 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
H A Dtegra124-cei-tk1-som.dts35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
40 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3740-0002+p3701-0008.dts83 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
90 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
98 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
106 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
116 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
H A Dtegra234-p3768-0000.dtsi145 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
153 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
163 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
174 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
/openbmc/linux/drivers/soc/tegra/
H A Dpmc.c3522 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3523 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3524 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3525 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3555 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3556 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3557 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3558 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3658 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3659 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
[all …]
/openbmc/u-boot/board/nvidia/p2771-0000/
H A Dp2771-0000.c40 /* Turn on MAX77620 LDO7 to 1.05V for PEX power */ in tegra_pcie_board_init()
41 debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__); in tegra_pcie_board_init()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.yaml74 avdd-pex-pll-supply:
77 hvdd-pex-pll-e-supply:
515 - avdd-pex-pll-supply
516 - hvdd-pex-pll-e-supply
532 avdd-pex-pll-supply = <&vdd_1v05_run>;
533 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
/openbmc/u-boot/board/nvidia/p2371-2180/
H A Dp2371-2180.c81 /* Turn on MAX77620 LDO1 to 1.05V for PEX power */ in tegra_pcie_board_init()
82 debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__); in tegra_pcie_board_init()

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