1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2edb47025SStefan Roese /* 3edb47025SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4edb47025SStefan Roese */ 5edb47025SStefan Roese 6edb47025SStefan Roese #ifndef _HIGH_SPEED_ENV_SPEC_H 7edb47025SStefan Roese #define _HIGH_SPEED_ENV_SPEC_H 8edb47025SStefan Roese 9edb47025SStefan Roese #include "seq_exec.h" 10edb47025SStefan Roese 11edb47025SStefan Roese /* 12edb47025SStefan Roese * For setting or clearing a certain bit (bit is a number between 0 and 31) 13edb47025SStefan Roese * in the data 14edb47025SStefan Roese */ 15edb47025SStefan Roese #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) 16edb47025SStefan Roese #define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit)))) 17edb47025SStefan Roese 18edb47025SStefan Roese #define MAX_SERDES_LANES 7 /* as in a39x */ 19edb47025SStefan Roese 20edb47025SStefan Roese /* Serdes revision */ 21edb47025SStefan Roese /* Serdes revision 1.2 (for A38x-Z1) */ 22edb47025SStefan Roese #define MV_SERDES_REV_1_2 0x0 23edb47025SStefan Roese /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */ 24edb47025SStefan Roese #define MV_SERDES_REV_2_1 0x1 25edb47025SStefan Roese #define MV_SERDES_REV_NA 0xff 26edb47025SStefan Roese 27edb47025SStefan Roese #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane)) 28edb47025SStefan Roese 29edb47025SStefan Roese #define PEX_X4_ENABLE_OFFS \ 30edb47025SStefan Roese (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31) 31edb47025SStefan Roese 32edb47025SStefan Roese /* Serdes lane types */ 33edb47025SStefan Roese enum serdes_type { 34edb47025SStefan Roese PEX0, 35edb47025SStefan Roese PEX1, 36edb47025SStefan Roese PEX2, 37edb47025SStefan Roese PEX3, 38edb47025SStefan Roese SATA0, 39edb47025SStefan Roese SATA1, 40edb47025SStefan Roese SATA2, 41edb47025SStefan Roese SATA3, 42edb47025SStefan Roese SGMII0, 43edb47025SStefan Roese SGMII1, 44edb47025SStefan Roese SGMII2, 45edb47025SStefan Roese QSGMII, 46edb47025SStefan Roese USB3_HOST0, 47edb47025SStefan Roese USB3_HOST1, 48edb47025SStefan Roese USB3_DEVICE, 49edb47025SStefan Roese SGMII3, 50edb47025SStefan Roese XAUI, 51edb47025SStefan Roese RXAUI, 52edb47025SStefan Roese DEFAULT_SERDES, 53edb47025SStefan Roese LAST_SERDES_TYPE 54edb47025SStefan Roese }; 55edb47025SStefan Roese 56edb47025SStefan Roese /* Serdes baud rates */ 57edb47025SStefan Roese enum serdes_speed { 58edb47025SStefan Roese SERDES_SPEED_1_25_GBPS, 59edb47025SStefan Roese SERDES_SPEED_1_5_GBPS, 60edb47025SStefan Roese SERDES_SPEED_2_5_GBPS, 61edb47025SStefan Roese SERDES_SPEED_3_GBPS, 62edb47025SStefan Roese SERDES_SPEED_3_125_GBPS, 63edb47025SStefan Roese SERDES_SPEED_5_GBPS, 64edb47025SStefan Roese SERDES_SPEED_6_GBPS, 65edb47025SStefan Roese SERDES_SPEED_6_25_GBPS, 66edb47025SStefan Roese LAST_SERDES_SPEED 67edb47025SStefan Roese }; 68edb47025SStefan Roese 69edb47025SStefan Roese /* Serdes modes */ 70edb47025SStefan Roese enum serdes_mode { 71edb47025SStefan Roese PEX_ROOT_COMPLEX_X1, 72edb47025SStefan Roese PEX_ROOT_COMPLEX_X4, 73edb47025SStefan Roese PEX_END_POINT_X1, 74edb47025SStefan Roese PEX_END_POINT_X4, 75edb47025SStefan Roese 76edb47025SStefan Roese SERDES_DEFAULT_MODE, /* not pex */ 77edb47025SStefan Roese 78edb47025SStefan Roese SERDES_LAST_MODE 79edb47025SStefan Roese }; 80edb47025SStefan Roese 81edb47025SStefan Roese struct serdes_map { 82edb47025SStefan Roese enum serdes_type serdes_type; 83edb47025SStefan Roese enum serdes_speed serdes_speed; 84edb47025SStefan Roese enum serdes_mode serdes_mode; 85edb47025SStefan Roese int swap_rx; 86edb47025SStefan Roese int swap_tx; 87edb47025SStefan Roese }; 88edb47025SStefan Roese 89edb47025SStefan Roese /* Serdes ref clock options */ 90edb47025SStefan Roese enum ref_clock { 91edb47025SStefan Roese REF_CLOCK_25MHZ, 92edb47025SStefan Roese REF_CLOCK_100MHZ, 93edb47025SStefan Roese REF_CLOCK_40MHZ, 94edb47025SStefan Roese REF_CLOCK_UNSUPPORTED 95edb47025SStefan Roese }; 96edb47025SStefan Roese 97edb47025SStefan Roese /* Serdes sequences */ 98edb47025SStefan Roese enum serdes_seq { 99edb47025SStefan Roese SATA_PORT_0_ONLY_POWER_UP_SEQ, 100edb47025SStefan Roese SATA_PORT_1_ONLY_POWER_UP_SEQ, 101edb47025SStefan Roese SATA_POWER_UP_SEQ, 102edb47025SStefan Roese SATA_1_5_SPEED_CONFIG_SEQ, 103edb47025SStefan Roese SATA_3_SPEED_CONFIG_SEQ, 104edb47025SStefan Roese SATA_6_SPEED_CONFIG_SEQ, 105edb47025SStefan Roese SATA_ELECTRICAL_CONFIG_SEQ, 106edb47025SStefan Roese SATA_TX_CONFIG_SEQ1, 107edb47025SStefan Roese SATA_PORT_0_ONLY_TX_CONFIG_SEQ, 108edb47025SStefan Roese SATA_PORT_1_ONLY_TX_CONFIG_SEQ, 109edb47025SStefan Roese SATA_TX_CONFIG_SEQ2, 110edb47025SStefan Roese 111edb47025SStefan Roese SGMII_POWER_UP_SEQ, 112edb47025SStefan Roese SGMII_1_25_SPEED_CONFIG_SEQ, 113edb47025SStefan Roese SGMII_3_125_SPEED_CONFIG_SEQ, 114edb47025SStefan Roese SGMII_ELECTRICAL_CONFIG_SEQ, 115edb47025SStefan Roese SGMII_TX_CONFIG_SEQ1, 116edb47025SStefan Roese SGMII_TX_CONFIG_SEQ2, 117edb47025SStefan Roese 118edb47025SStefan Roese PEX_POWER_UP_SEQ, 119edb47025SStefan Roese PEX_2_5_SPEED_CONFIG_SEQ, 120edb47025SStefan Roese PEX_5_SPEED_CONFIG_SEQ, 121edb47025SStefan Roese PEX_ELECTRICAL_CONFIG_SEQ, 122edb47025SStefan Roese PEX_TX_CONFIG_SEQ1, 123edb47025SStefan Roese PEX_TX_CONFIG_SEQ2, 124edb47025SStefan Roese PEX_TX_CONFIG_SEQ3, 125edb47025SStefan Roese PEX_BY_4_CONFIG_SEQ, 126edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_25MHZ_SEQ, 127edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_100MHZ_SEQ, 128edb47025SStefan Roese PEX_CONFIG_REF_CLOCK_40MHZ_SEQ, 129edb47025SStefan Roese 130edb47025SStefan Roese USB3_POWER_UP_SEQ, 131edb47025SStefan Roese USB3_HOST_SPEED_CONFIG_SEQ, 132edb47025SStefan Roese USB3_DEVICE_SPEED_CONFIG_SEQ, 133edb47025SStefan Roese USB3_ELECTRICAL_CONFIG_SEQ, 134edb47025SStefan Roese USB3_TX_CONFIG_SEQ1, 135edb47025SStefan Roese USB3_TX_CONFIG_SEQ2, 136edb47025SStefan Roese USB3_TX_CONFIG_SEQ3, 137edb47025SStefan Roese USB3_DEVICE_CONFIG_SEQ, 138edb47025SStefan Roese 139edb47025SStefan Roese USB2_POWER_UP_SEQ, 140edb47025SStefan Roese 141edb47025SStefan Roese SERDES_POWER_DOWN_SEQ, 142edb47025SStefan Roese 143edb47025SStefan Roese SGMII3_POWER_UP_SEQ, 144edb47025SStefan Roese SGMII3_1_25_SPEED_CONFIG_SEQ, 145edb47025SStefan Roese SGMII3_TX_CONFIG_SEQ1, 146edb47025SStefan Roese SGMII3_TX_CONFIG_SEQ2, 147edb47025SStefan Roese 148edb47025SStefan Roese QSGMII_POWER_UP_SEQ, 149edb47025SStefan Roese QSGMII_5_SPEED_CONFIG_SEQ, 150edb47025SStefan Roese QSGMII_ELECTRICAL_CONFIG_SEQ, 151edb47025SStefan Roese QSGMII_TX_CONFIG_SEQ1, 152edb47025SStefan Roese QSGMII_TX_CONFIG_SEQ2, 153edb47025SStefan Roese 154edb47025SStefan Roese XAUI_POWER_UP_SEQ, 155edb47025SStefan Roese XAUI_3_125_SPEED_CONFIG_SEQ, 156edb47025SStefan Roese XAUI_ELECTRICAL_CONFIG_SEQ, 157edb47025SStefan Roese XAUI_TX_CONFIG_SEQ1, 158edb47025SStefan Roese XAUI_TX_CONFIG_SEQ2, 159edb47025SStefan Roese 160edb47025SStefan Roese RXAUI_POWER_UP_SEQ, 161edb47025SStefan Roese RXAUI_6_25_SPEED_CONFIG_SEQ, 162edb47025SStefan Roese RXAUI_ELECTRICAL_CONFIG_SEQ, 163edb47025SStefan Roese RXAUI_TX_CONFIG_SEQ1, 164edb47025SStefan Roese RXAUI_TX_CONFIG_SEQ2, 165edb47025SStefan Roese 166edb47025SStefan Roese SERDES_LAST_SEQ 167edb47025SStefan Roese }; 168edb47025SStefan Roese 169edb47025SStefan Roese /* The different sequence types for PEX and USB3 */ 170edb47025SStefan Roese enum { 171edb47025SStefan Roese PEX, 172edb47025SStefan Roese USB3, 173edb47025SStefan Roese LAST_PEX_USB_SEQ_TYPE 174edb47025SStefan Roese }; 175edb47025SStefan Roese 176edb47025SStefan Roese enum { 177edb47025SStefan Roese PEXSERDES_SPEED_2_5_GBPS, 178edb47025SStefan Roese PEXSERDES_SPEED_5_GBPS, 179edb47025SStefan Roese USB3SERDES_SPEED_5_GBPS_HOST, 180edb47025SStefan Roese USB3SERDES_SPEED_5_GBPS_DEVICE, 181edb47025SStefan Roese LAST_PEX_USB_SPEED_SEQ_TYPE 182edb47025SStefan Roese }; 183edb47025SStefan Roese 184edb47025SStefan Roese /* The different sequence types for SATA and SGMII */ 185edb47025SStefan Roese enum { 186edb47025SStefan Roese SATA, 187edb47025SStefan Roese SGMII, 188edb47025SStefan Roese SGMII_3_125, 189edb47025SStefan Roese LAST_SATA_SGMII_SEQ_TYPE 190edb47025SStefan Roese }; 191edb47025SStefan Roese 192edb47025SStefan Roese enum { 193edb47025SStefan Roese QSGMII_SEQ_IDX, 194edb47025SStefan Roese LAST_QSGMII_SEQ_TYPE 195edb47025SStefan Roese }; 196edb47025SStefan Roese 197edb47025SStefan Roese enum { 198edb47025SStefan Roese XAUI_SEQ_IDX, 199edb47025SStefan Roese RXAUI_SEQ_IDX, 200edb47025SStefan Roese LAST_XAUI_RXAUI_SEQ_TYPE 201edb47025SStefan Roese }; 202edb47025SStefan Roese 203edb47025SStefan Roese enum { 204edb47025SStefan Roese SATASERDES_SPEED_1_5_GBPS, 205edb47025SStefan Roese SATASERDES_SPEED_3_GBPS, 206edb47025SStefan Roese SATASERDES_SPEED_6_GBPS, 207edb47025SStefan Roese SGMIISERDES_SPEED_1_25_GBPS, 208edb47025SStefan Roese SGMIISERDES_SPEED_3_125_GBPS, 209edb47025SStefan Roese LAST_SATA_SGMII_SPEED_SEQ_TYPE 210edb47025SStefan Roese }; 211edb47025SStefan Roese 212edb47025SStefan Roese extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 213edb47025SStefan Roese extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; 214edb47025SStefan Roese 215edb47025SStefan Roese u8 hws_ctrl_serdes_rev_get(void); 216edb47025SStefan Roese int mv_update_serdes_select_phy_mode_seq(void); 217490753acSKevin Smith int hws_board_topology_load(struct serdes_map **serdes_map, u8 *count); 218edb47025SStefan Roese enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, 219edb47025SStefan Roese enum serdes_speed baud_rate); 220edb47025SStefan Roese int hws_serdes_seq_init(void); 221edb47025SStefan Roese int hws_serdes_seq_db_init(void); 222490753acSKevin Smith int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count); 223edb47025SStefan Roese int hws_ctrl_high_speed_serdes_phy_config(void); 224edb47025SStefan Roese int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, 225edb47025SStefan Roese enum serdes_type serdes_type, 226edb47025SStefan Roese enum serdes_speed baud_rate, 227edb47025SStefan Roese enum serdes_mode serdes_mode, 228edb47025SStefan Roese enum ref_clock ref_clock); 229edb47025SStefan Roese int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up, 230edb47025SStefan Roese enum serdes_type serdes_type, 231edb47025SStefan Roese enum serdes_speed baud_rate, 232edb47025SStefan Roese enum serdes_mode serdes_mode, 233edb47025SStefan Roese enum ref_clock ref_clock); 234edb47025SStefan Roese u32 hws_serdes_silicon_ref_clock_get(void); 235edb47025SStefan Roese int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type, 236edb47025SStefan Roese enum ref_clock *ref_clock); 237edb47025SStefan Roese int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, 238edb47025SStefan Roese enum ref_clock ref_clock); 239490753acSKevin Smith int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count); 240edb47025SStefan Roese u32 hws_serdes_get_phy_selector_val(int serdes_num, 241edb47025SStefan Roese enum serdes_type serdes_type); 242edb47025SStefan Roese u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type); 243edb47025SStefan Roese u32 hws_serdes_get_max_lane(void); 244edb47025SStefan Roese int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset, 245edb47025SStefan Roese u32 *unit_base_reg, u32 *unit_offset); 246490753acSKevin Smith int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count); 247edb47025SStefan Roese u32 hws_get_physical_serdes_num(u32 serdes_num); 248edb47025SStefan Roese int hws_is_serdes_active(u8 lane_num); 249edb47025SStefan Roese 250edb47025SStefan Roese #endif /* _HIGH_SPEED_ENV_SPEC_H */ 251