1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0
229b103c7SStefan Roese /*
329b103c7SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates
429b103c7SStefan Roese */
529b103c7SStefan Roese
629b103c7SStefan Roese #include <common.h>
729b103c7SStefan Roese #include <i2c.h>
829b103c7SStefan Roese #include <spl.h>
929b103c7SStefan Roese #include <asm/io.h>
1029b103c7SStefan Roese #include <asm/arch/cpu.h>
1129b103c7SStefan Roese #include <asm/arch/soc.h>
1229b103c7SStefan Roese
1329b103c7SStefan Roese #include "high_speed_env_spec.h"
1429b103c7SStefan Roese #include "board_env_spec.h"
1529b103c7SStefan Roese
16d374e90bSUwe Kleine-König #define SERDES_VERSION "2.1.5"
1729b103c7SStefan Roese #define ENDED_OK "High speed PHY - Ended Successfully\n"
1829b103c7SStefan Roese
1929b103c7SStefan Roese static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
2029b103c7SStefan Roese
2129b103c7SStefan Roese extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
2229b103c7SStefan Roese
2329b103c7SStefan Roese extern u8 rd78460gp_twsi_dev[];
2429b103c7SStefan Roese extern u8 db88f78xx0rev2_twsi_dev[];
2529b103c7SStefan Roese
2629b103c7SStefan Roese u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
2729b103c7SStefan Roese int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
2829b103c7SStefan Roese int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
2929b103c7SStefan Roese
3029b103c7SStefan Roese #define MV_BOARD_PEX_MODULE_ADDR 0x23
3129b103c7SStefan Roese #define MV_BOARD_PEX_MODULE_ID 1
3229b103c7SStefan Roese #define MV_BOARD_ETM_MODULE_ID 2
3329b103c7SStefan Roese
3429b103c7SStefan Roese #define PEX_MODULE_DETECT 1
3529b103c7SStefan Roese #define ETM_MODULE_DETECT 2
3629b103c7SStefan Roese
3729b103c7SStefan Roese #define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
3829b103c7SStefan Roese #define PEX_CAPABILITY_GET(satr) (satr & 1)
3929b103c7SStefan Roese #define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
4029b103c7SStefan Roese
4129b103c7SStefan Roese /* Static parametes */
4229b103c7SStefan Roese static int config_module;
4329b103c7SStefan Roese static int switch_module;
4429b103c7SStefan Roese
4529b103c7SStefan Roese /* Local function */
board_id_get(void)4629b103c7SStefan Roese static u32 board_id_get(void)
4729b103c7SStefan Roese {
4829b103c7SStefan Roese #if defined(CONFIG_DB_88F78X60)
4929b103c7SStefan Roese return DB_88F78XX0_BP_ID;
5029b103c7SStefan Roese #elif defined(CONFIG_RD_88F78460_SERVER)
5129b103c7SStefan Roese return RD_78460_SERVER_ID;
5229b103c7SStefan Roese #elif defined(CONFIG_RD_78460_SERVER_REV2)
5329b103c7SStefan Roese return RD_78460_SERVER_REV2_ID;
5429b103c7SStefan Roese #elif defined(CONFIG_DB_78X60_PCAC)
5529b103c7SStefan Roese return DB_78X60_PCAC_ID;
5629b103c7SStefan Roese #elif defined(CONFIG_DB_88F78X60_REV2)
5729b103c7SStefan Roese return DB_88F78XX0_BP_REV2_ID;
5829b103c7SStefan Roese #elif defined(CONFIG_RD_78460_NAS)
5929b103c7SStefan Roese return RD_78460_NAS_ID;
6029b103c7SStefan Roese #elif defined(CONFIG_DB_78X60_AMC)
6129b103c7SStefan Roese return DB_78X60_AMC_ID;
6229b103c7SStefan Roese #elif defined(CONFIG_DB_78X60_PCAC_REV2)
6329b103c7SStefan Roese return DB_78X60_PCAC_REV2_ID;
6429b103c7SStefan Roese #elif defined(CONFIG_DB_784MP_GP)
6529b103c7SStefan Roese return DB_784MP_GP_ID;
6629b103c7SStefan Roese #elif defined(CONFIG_RD_78460_CUSTOMER)
6729b103c7SStefan Roese return RD_78460_CUSTOMER_ID;
6829b103c7SStefan Roese #else
6929b103c7SStefan Roese /*
7029b103c7SStefan Roese * Return 0 here for custom board as this should not be used
7129b103c7SStefan Roese * for custom boards.
7229b103c7SStefan Roese */
7329b103c7SStefan Roese return 0;
7429b103c7SStefan Roese #endif
7529b103c7SStefan Roese }
7629b103c7SStefan Roese
board_sat_r_get(u8 dev_num,u8 reg)77beadff17SPhil Sutter __weak u8 board_sat_r_get(u8 dev_num, u8 reg)
7829b103c7SStefan Roese {
7929b103c7SStefan Roese u8 data;
8029b103c7SStefan Roese u8 *dev;
8129b103c7SStefan Roese u32 board_id = board_id_get();
8229b103c7SStefan Roese int ret;
8329b103c7SStefan Roese
8429b103c7SStefan Roese switch (board_id) {
85beadff17SPhil Sutter case DB_78X60_AMC_ID:
86beadff17SPhil Sutter case DB_78X60_PCAC_REV2_ID:
87beadff17SPhil Sutter case RD_78460_CUSTOMER_ID:
88beadff17SPhil Sutter case RD_78460_SERVER_ID:
89beadff17SPhil Sutter case RD_78460_SERVER_REV2_ID:
90beadff17SPhil Sutter case DB_78X60_PCAC_ID:
91beadff17SPhil Sutter return (0x1 << 1) | 1;
92beadff17SPhil Sutter case FPGA_88F78XX0_ID:
93beadff17SPhil Sutter case RD_78460_NAS_ID:
94beadff17SPhil Sutter return (0x0 << 1) | 1;
9529b103c7SStefan Roese case DB_784MP_GP_ID:
9629b103c7SStefan Roese dev = rd78460gp_twsi_dev;
9729b103c7SStefan Roese
9829b103c7SStefan Roese break;
9929b103c7SStefan Roese case DB_88F78XX0_BP_ID:
10029b103c7SStefan Roese case DB_88F78XX0_BP_REV2_ID:
10129b103c7SStefan Roese dev = db88f78xx0rev2_twsi_dev;
10229b103c7SStefan Roese break;
10329b103c7SStefan Roese
10429b103c7SStefan Roese default:
10529b103c7SStefan Roese return 0;
10629b103c7SStefan Roese }
10729b103c7SStefan Roese
10829b103c7SStefan Roese /* Read MPP module ID */
109beadff17SPhil Sutter i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
11029b103c7SStefan Roese ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
11129b103c7SStefan Roese if (ret)
11229b103c7SStefan Roese return MV_ERROR;
11329b103c7SStefan Roese
11429b103c7SStefan Roese return data;
11529b103c7SStefan Roese }
11629b103c7SStefan Roese
board_modules_scan(void)11729b103c7SStefan Roese static int board_modules_scan(void)
11829b103c7SStefan Roese {
11929b103c7SStefan Roese u8 val;
12029b103c7SStefan Roese u32 board_id = board_id_get();
12129b103c7SStefan Roese int ret;
12229b103c7SStefan Roese
12329b103c7SStefan Roese /* Perform scan only for DB board */
12429b103c7SStefan Roese if ((board_id == DB_88F78XX0_BP_ID) ||
12529b103c7SStefan Roese (board_id == DB_88F78XX0_BP_REV2_ID)) {
12629b103c7SStefan Roese /* reset modules flags */
12729b103c7SStefan Roese config_module = 0;
12829b103c7SStefan Roese
12929b103c7SStefan Roese i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
13029b103c7SStefan Roese
13129b103c7SStefan Roese /* SERDES module (only PEX model is supported now) */
13229b103c7SStefan Roese ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
13329b103c7SStefan Roese if (ret)
13429b103c7SStefan Roese return MV_ERROR;
13529b103c7SStefan Roese
13629b103c7SStefan Roese if (val == MV_BOARD_PEX_MODULE_ID)
13729b103c7SStefan Roese config_module = PEX_MODULE_DETECT;
13829b103c7SStefan Roese if (val == MV_BOARD_ETM_MODULE_ID)
13929b103c7SStefan Roese config_module = ETM_MODULE_DETECT;
14029b103c7SStefan Roese } else if (board_id == RD_78460_NAS_ID) {
14129b103c7SStefan Roese switch_module = 0;
14229b103c7SStefan Roese if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
14329b103c7SStefan Roese switch_module = 1;
14429b103c7SStefan Roese }
14529b103c7SStefan Roese
14629b103c7SStefan Roese return MV_OK;
14729b103c7SStefan Roese }
14829b103c7SStefan Roese
pex_max_unit_get(void)14929b103c7SStefan Roese u32 pex_max_unit_get(void)
15029b103c7SStefan Roese {
15129b103c7SStefan Roese /*
15229b103c7SStefan Roese * TODO:
15329b103c7SStefan Roese * Right now only MV78460 is supported. Other SoC's might need
15429b103c7SStefan Roese * a different value here.
15529b103c7SStefan Roese */
15629b103c7SStefan Roese return MV_PEX_MAX_UNIT;
15729b103c7SStefan Roese }
15829b103c7SStefan Roese
pex_max_if_get(void)15929b103c7SStefan Roese u32 pex_max_if_get(void)
16029b103c7SStefan Roese {
16129b103c7SStefan Roese /*
16229b103c7SStefan Roese * TODO:
16329b103c7SStefan Roese * Right now only MV78460 is supported. Other SoC's might need
16429b103c7SStefan Roese * a different value here.
16529b103c7SStefan Roese */
16629b103c7SStefan Roese return MV_PEX_MAX_IF;
16729b103c7SStefan Roese }
16829b103c7SStefan Roese
board_cpu_freq_get(void)16929b103c7SStefan Roese u8 board_cpu_freq_get(void)
17029b103c7SStefan Roese {
17129b103c7SStefan Roese u32 sar;
17229b103c7SStefan Roese u32 sar_msb;
17329b103c7SStefan Roese
17429b103c7SStefan Roese sar = reg_read(MPP_SAMPLE_AT_RESET(0));
17529b103c7SStefan Roese sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
17629b103c7SStefan Roese return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
17729b103c7SStefan Roese }
17829b103c7SStefan Roese
board_serdes_cfg_get(u8 pex_mode)17929b103c7SStefan Roese __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
18029b103c7SStefan Roese {
18129b103c7SStefan Roese u32 board_id;
18229b103c7SStefan Roese u32 serdes_cfg_val = 0; /* default */
18329b103c7SStefan Roese
18429b103c7SStefan Roese board_id = board_id_get();
18529b103c7SStefan Roese
18629b103c7SStefan Roese switch (board_id) {
18729b103c7SStefan Roese case DB_784MP_GP_ID:
18829b103c7SStefan Roese serdes_cfg_val = 0;
18929b103c7SStefan Roese break;
19029b103c7SStefan Roese }
19129b103c7SStefan Roese
19229b103c7SStefan Roese return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
19329b103c7SStefan Roese }
19429b103c7SStefan Roese
ctrl_model_get(void)19529b103c7SStefan Roese u16 ctrl_model_get(void)
19629b103c7SStefan Roese {
197bf0db8b8SStefan Roese /*
198bf0db8b8SStefan Roese * SoC version can't be autodetected. So we need to rely on a define
199bf0db8b8SStefan Roese * from the config system here.
200bf0db8b8SStefan Roese */
2016202953dSPhil Sutter #if defined(CONFIG_MV78230)
2026202953dSPhil Sutter return MV_78230_DEV_ID;
2036202953dSPhil Sutter #elif defined(CONFIG_MV78260)
204bf0db8b8SStefan Roese return MV_78260_DEV_ID;
205bf0db8b8SStefan Roese #else
20629b103c7SStefan Roese return MV_78460_DEV_ID;
207bf0db8b8SStefan Roese #endif
20829b103c7SStefan Roese }
20929b103c7SStefan Roese
get_line_cfg(u32 line_num,MV_BIN_SERDES_CFG * info)21029b103c7SStefan Roese u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
21129b103c7SStefan Roese {
21229b103c7SStefan Roese if (line_num < 8)
21329b103c7SStefan Roese return (info->line0_7 >> (line_num << 2)) & 0xF;
21429b103c7SStefan Roese else
21529b103c7SStefan Roese return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
21629b103c7SStefan Roese }
21729b103c7SStefan Roese
serdes_max_lines_get(void)218bf0db8b8SStefan Roese static int serdes_max_lines_get(void)
219bf0db8b8SStefan Roese {
220bf0db8b8SStefan Roese switch (ctrl_model_get()) {
2216202953dSPhil Sutter case MV_78230_DEV_ID:
2226202953dSPhil Sutter return 7;
223bf0db8b8SStefan Roese case MV_78260_DEV_ID:
224bf0db8b8SStefan Roese return 12;
225bf0db8b8SStefan Roese case MV_78460_DEV_ID:
226bf0db8b8SStefan Roese return 16;
227bf0db8b8SStefan Roese }
228bf0db8b8SStefan Roese
229bf0db8b8SStefan Roese return 0;
230bf0db8b8SStefan Roese }
231bf0db8b8SStefan Roese
2322399e401SStefan Roese /*
2332399e401SStefan Roese * Tests have shown that on some boards the default width of the
2342399e401SStefan Roese * configuration pulse for the PEX link detection might lead to
2352399e401SStefan Roese * non-established PCIe links (link down). Especially under certain
2362399e401SStefan Roese * conditions (higher temperature) and with specific PCIe devices.
2372399e401SStefan Roese * To enable a board-specific detection pulse width this weak
2382399e401SStefan Roese * array "serdes_pex_pulse_width[4]" is introduced which can be
2392399e401SStefan Roese * overwritten if needed by a board-specific version. If the board
2402399e401SStefan Roese * code does not provide a non-weak version of this variable, the
2412399e401SStefan Roese * default value will be used. So nothing is changed from the
2422399e401SStefan Roese * current setup on the supported board.
2432399e401SStefan Roese */
2442399e401SStefan Roese __weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 };
2452399e401SStefan Roese
serdes_phy_config(void)24629b103c7SStefan Roese int serdes_phy_config(void)
24729b103c7SStefan Roese {
24829b103c7SStefan Roese int status = MV_OK;
24929b103c7SStefan Roese u32 line_cfg;
25029b103c7SStefan Roese u8 line_num;
25129b103c7SStefan Roese /* addr/value for each line @ every setup step */
25229b103c7SStefan Roese u32 addr[16][11], val[16][11];
25329b103c7SStefan Roese u8 pex_unit, pex_line_num;
25429b103c7SStefan Roese u8 sgmii_port = 0;
25529b103c7SStefan Roese u32 tmp;
25629b103c7SStefan Roese u32 in_direct;
25729b103c7SStefan Roese u8 max_serdes_lines;
25829b103c7SStefan Roese MV_BIN_SERDES_CFG *info;
25929b103c7SStefan Roese u8 satr11;
26029b103c7SStefan Roese u8 sata_port;
26129b103c7SStefan Roese u8 freq;
26229b103c7SStefan Roese u8 device_rev;
26329b103c7SStefan Roese u32 rx_high_imp_mode;
26429b103c7SStefan Roese u16 ctrl_mode;
26529b103c7SStefan Roese u32 pex_if;
26629b103c7SStefan Roese u32 pex_if_num;
26729b103c7SStefan Roese
26829b103c7SStefan Roese /*
269bf0db8b8SStefan Roese * Get max. serdes lines count
27029b103c7SStefan Roese */
271bf0db8b8SStefan Roese max_serdes_lines = serdes_max_lines_get();
27229b103c7SStefan Roese if (max_serdes_lines == 0)
27329b103c7SStefan Roese return MV_OK;
27429b103c7SStefan Roese
27529b103c7SStefan Roese satr11 = board_sat_r_get(1, 1);
27629b103c7SStefan Roese if ((u8) MV_ERROR == (u8) satr11)
27729b103c7SStefan Roese return MV_ERROR;
27829b103c7SStefan Roese
27929b103c7SStefan Roese board_modules_scan();
28029b103c7SStefan Roese memset(addr, 0, sizeof(addr));
28129b103c7SStefan Roese memset(val, 0, sizeof(val));
28229b103c7SStefan Roese
28329b103c7SStefan Roese /* Check if DRAM is already initialized */
28429b103c7SStefan Roese if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
28529b103c7SStefan Roese (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
28629b103c7SStefan Roese DEBUG_INIT_S("High speed PHY - Version: ");
287d374e90bSUwe Kleine-König DEBUG_INIT_S(SERDES_VERSION);
28829b103c7SStefan Roese DEBUG_INIT_S(" - 2nd boot - Skip\n");
28929b103c7SStefan Roese return MV_OK;
29029b103c7SStefan Roese }
29129b103c7SStefan Roese DEBUG_INIT_S("High speed PHY - Version: ");
292d374e90bSUwe Kleine-König DEBUG_INIT_S(SERDES_VERSION);
29329b103c7SStefan Roese DEBUG_INIT_S(" (COM-PHY-V20)\n");
29429b103c7SStefan Roese
29529b103c7SStefan Roese /*
29629b103c7SStefan Roese * AVS : disable AVS for frequency less than 1333
29729b103c7SStefan Roese */
29829b103c7SStefan Roese freq = board_cpu_freq_get();
29929b103c7SStefan Roese device_rev = mv_ctrl_rev_get();
30029b103c7SStefan Roese
30129b103c7SStefan Roese if (device_rev == 2) { /* for B0 only */
30229b103c7SStefan Roese u32 cpu_avs;
30329b103c7SStefan Roese u8 fabric_freq;
30429b103c7SStefan Roese cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
30529b103c7SStefan Roese DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
30629b103c7SStefan Roese cpu_avs &= ~(1 << 9);
30729b103c7SStefan Roese
30829b103c7SStefan Roese if ((0x4 == freq) || (0xB == freq)) {
30929b103c7SStefan Roese u32 tmp2;
31029b103c7SStefan Roese
31129b103c7SStefan Roese tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
31229b103c7SStefan Roese DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
31329b103c7SStefan Roese /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
31429b103c7SStefan Roese tmp2 |= 0x0FF;
31529b103c7SStefan Roese reg_write(CPU_AVS_CONTROL0_REG, tmp2);
31629b103c7SStefan Roese DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
31729b103c7SStefan Roese cpu_avs |= (1 << 9); /* cpu avs enable */
31829b103c7SStefan Roese cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
31929b103c7SStefan Roese fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
32029b103c7SStefan Roese SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
32129b103c7SStefan Roese if ((0xB == freq) && (5 == fabric_freq)) {
32229b103c7SStefan Roese u32 core_avs;
32329b103c7SStefan Roese
32429b103c7SStefan Roese core_avs = reg_read(CORE_AVS_CONTROL_0REG);
32529b103c7SStefan Roese DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
32629b103c7SStefan Roese
32729b103c7SStefan Roese /*
32829b103c7SStefan Roese * Set core lower limit = 0.9V &
32929b103c7SStefan Roese * core upper limit = 0.9125V
33029b103c7SStefan Roese */
33129b103c7SStefan Roese core_avs &= ~(0xff);
33229b103c7SStefan Roese core_avs |= 0x0E;
33329b103c7SStefan Roese reg_write(CORE_AVS_CONTROL_0REG, core_avs);
33429b103c7SStefan Roese DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
33529b103c7SStefan Roese
33629b103c7SStefan Roese core_avs = reg_read(CORE_AVS_CONTROL_2REG);
33729b103c7SStefan Roese DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
33829b103c7SStefan Roese core_avs |= (1 << 9); /* core AVS enable */
33929b103c7SStefan Roese reg_write(CORE_AVS_CONTROL_2REG, core_avs);
34029b103c7SStefan Roese DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
34129b103c7SStefan Roese
34229b103c7SStefan Roese tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
34329b103c7SStefan Roese DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
34429b103c7SStefan Roese tmp2);
34529b103c7SStefan Roese tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
34629b103c7SStefan Roese reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
34729b103c7SStefan Roese DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
34829b103c7SStefan Roese tmp2);
34929b103c7SStefan Roese }
35029b103c7SStefan Roese }
35129b103c7SStefan Roese reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
35229b103c7SStefan Roese DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
35329b103c7SStefan Roese }
35429b103c7SStefan Roese
35529b103c7SStefan Roese info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
35629b103c7SStefan Roese
35729b103c7SStefan Roese if (info == NULL) {
35829b103c7SStefan Roese DEBUG_INIT_S("Hight speed PHY Error #1\n");
35929b103c7SStefan Roese return MV_ERROR;
36029b103c7SStefan Roese }
361a22bbfdaSxypron.glpk@gmx.de DEBUG_INIT_FULL_S("info->line0_7= 0x");
362a22bbfdaSxypron.glpk@gmx.de DEBUG_INIT_FULL_D(info->line0_7, 8);
363a22bbfdaSxypron.glpk@gmx.de DEBUG_INIT_FULL_S(" info->line8_15= 0x");
364a22bbfdaSxypron.glpk@gmx.de DEBUG_INIT_FULL_D(info->line8_15, 8);
365a22bbfdaSxypron.glpk@gmx.de DEBUG_INIT_FULL_S("\n");
36629b103c7SStefan Roese
36729b103c7SStefan Roese if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
36829b103c7SStefan Roese DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
36929b103c7SStefan Roese reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
37029b103c7SStefan Roese DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
37129b103c7SStefan Roese info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
37229b103c7SStefan Roese mdelay(100);
37329b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
37429b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
37529b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
37629b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
37729b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
37829b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
37929b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
38029b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
38129b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
38229b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
38329b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
38429b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
38529b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
38629b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
38729b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
38829b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
38929b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
39029b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
39129b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
39229b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
39329b103c7SStefan Roese }
39429b103c7SStefan Roese
39529b103c7SStefan Roese /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
39629b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
39729b103c7SStefan Roese for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
39829b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
39929b103c7SStefan Roese continue;
40029b103c7SStefan Roese
40129b103c7SStefan Roese /* 1. GLOB_CLK_CTRL Reset and Clock Control */
40229b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
40329b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
40429b103c7SStefan Roese
40529b103c7SStefan Roese /* 2. GLOB_TEST_CTRL Test Mode Control */
40629b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
40729b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
40829b103c7SStefan Roese (0xC2 << 16) | 0x200);
40929b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
41029b103c7SStefan Roese (0xC2 << 16) | 0x200);
41129b103c7SStefan Roese }
41229b103c7SStefan Roese
41329b103c7SStefan Roese /* 3. GLOB_CLK_SRC_LO Clock Source Low */
41429b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
41529b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
41629b103c7SStefan Roese (0xC3 << 16) | 0x0F);
41729b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
41829b103c7SStefan Roese (0xC3 << 16) | 0x0F);
41929b103c7SStefan Roese }
42029b103c7SStefan Roese
42129b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
42229b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
42329b103c7SStefan Roese (0xC5 << 16) | 0x11F);
42429b103c7SStefan Roese }
42529b103c7SStefan Roese
42629b103c7SStefan Roese /*
42729b103c7SStefan Roese * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
42829b103c7SStefan Roese * PU_RX,PU_TX. (bits[12:5])
42929b103c7SStefan Roese */
43029b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
43129b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
43229b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
43329b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
43429b103c7SStefan Roese continue;
43529b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
43629b103c7SStefan Roese continue;
43729b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
43829b103c7SStefan Roese switch (line_num) {
43929b103c7SStefan Roese case 4:
44029b103c7SStefan Roese case 6:
44129b103c7SStefan Roese sata_port = 0;
44229b103c7SStefan Roese break;
44329b103c7SStefan Roese case 5:
44429b103c7SStefan Roese sata_port = 1;
44529b103c7SStefan Roese break;
44629b103c7SStefan Roese default:
44729b103c7SStefan Roese DEBUG_INIT_C
44829b103c7SStefan Roese ("SATA port error for serdes line: ",
44929b103c7SStefan Roese line_num, 2);
45029b103c7SStefan Roese return MV_ERROR;
45129b103c7SStefan Roese }
45229b103c7SStefan Roese tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
45329b103c7SStefan Roese DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
45429b103c7SStefan Roese tmp &= ~((0x1ff << 5) | 0x7);
45529b103c7SStefan Roese tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
45629b103c7SStefan Roese (0x11 << 5) : 0x0;
45729b103c7SStefan Roese
45829b103c7SStefan Roese reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
45929b103c7SStefan Roese DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
46029b103c7SStefan Roese }
46129b103c7SStefan Roese
46229b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
46329b103c7SStefan Roese /*
46429b103c7SStefan Roese * 4) Configure the desire PIN_PHY_GEN and do power
46529b103c7SStefan Roese * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
46629b103c7SStefan Roese */
46729b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_CFG_REG(0));
46829b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
46929b103c7SStefan Roese tmp &= ~((0x1ff << 5) | 0x7);
47029b103c7SStefan Roese tmp |= 0x660;
47129b103c7SStefan Roese reg_write(SGMII_SERDES_CFG_REG(0), tmp);
47229b103c7SStefan Roese DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
47329b103c7SStefan Roese continue;
47429b103c7SStefan Roese }
47529b103c7SStefan Roese
47629b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
47729b103c7SStefan Roese sgmii_port = 0;
47829b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
47929b103c7SStefan Roese sgmii_port = 1;
48029b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
48129b103c7SStefan Roese sgmii_port = 2;
48229b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
48329b103c7SStefan Roese sgmii_port = 3;
48429b103c7SStefan Roese else
48529b103c7SStefan Roese continue;
48629b103c7SStefan Roese
48729b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
48829b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
48929b103c7SStefan Roese tmp &= ~((0x1ff << 5) | 0x7);
49029b103c7SStefan Roese tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
49129b103c7SStefan Roese (0x88 << 5) : (0x66 << 5));
49229b103c7SStefan Roese reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
49329b103c7SStefan Roese DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
49429b103c7SStefan Roese }
49529b103c7SStefan Roese
49629b103c7SStefan Roese /* Step 3 - QSGMII enable */
49729b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
49829b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
49929b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
50029b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
50129b103c7SStefan Roese /* QSGMII Active bit set to true */
50229b103c7SStefan Roese tmp = reg_read(QSGMII_CONTROL_1_REG);
50329b103c7SStefan Roese DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
50429b103c7SStefan Roese tmp |= (1 << 30);
50529b103c7SStefan Roese #ifdef ERRATA_GL_6572255
50629b103c7SStefan Roese tmp |= (1 << 27);
50729b103c7SStefan Roese #endif
50829b103c7SStefan Roese reg_write(QSGMII_CONTROL_1_REG, tmp);
50929b103c7SStefan Roese DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
51029b103c7SStefan Roese }
51129b103c7SStefan Roese }
51229b103c7SStefan Roese
51329b103c7SStefan Roese /* Step 4 - configure SERDES MUXes */
51429b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
51529b103c7SStefan Roese if (config_module & ETM_MODULE_DETECT) {
51629b103c7SStefan Roese reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
51729b103c7SStefan Roese DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
51829b103c7SStefan Roese } else {
51929b103c7SStefan Roese reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
52029b103c7SStefan Roese DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
52129b103c7SStefan Roese }
52229b103c7SStefan Roese reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
52329b103c7SStefan Roese DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
52429b103c7SStefan Roese
52529b103c7SStefan Roese /* Step 5: Activate the RX High Impedance Mode */
52629b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
52729b103c7SStefan Roese rx_high_imp_mode = 0x8080;
52829b103c7SStefan Roese if (device_rev == 2) /* for B0 only */
52929b103c7SStefan Roese rx_high_imp_mode |= 4;
53029b103c7SStefan Roese
53129b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
53229b103c7SStefan Roese /* for each serdes lane */
53329b103c7SStefan Roese DEBUG_INIT_FULL_S("SERDES ");
53429b103c7SStefan Roese DEBUG_INIT_FULL_D_10(line_num, 2);
53529b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
53629b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
53729b103c7SStefan Roese DEBUG_INIT_FULL_S(" unconnected ***\n");
53829b103c7SStefan Roese continue;
53929b103c7SStefan Roese }
54029b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
54129b103c7SStefan Roese pex_unit = line_num >> 2;
54229b103c7SStefan Roese pex_line_num = line_num % 4;
54329b103c7SStefan Roese DEBUG_INIT_FULL_S(" - PEX unit ");
54429b103c7SStefan Roese DEBUG_INIT_FULL_D_10(pex_unit, 1);
54529b103c7SStefan Roese DEBUG_INIT_FULL_S(" line= ");
54629b103c7SStefan Roese DEBUG_INIT_FULL_D_10(pex_line_num, 1);
54729b103c7SStefan Roese DEBUG_INIT_FULL_S("\n");
54829b103c7SStefan Roese
54929b103c7SStefan Roese /* Needed for PEX_PHY_ACCESS_REG macro */
55029b103c7SStefan Roese if ((line_num > 7) &&
55129b103c7SStefan Roese (info->pex_mode[3] == PEX_BUS_MODE_X8))
55229b103c7SStefan Roese /* lines 8 - 15 are belong to PEX3 in x8 mode */
55329b103c7SStefan Roese pex_unit = 3;
55429b103c7SStefan Roese
55529b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
55629b103c7SStefan Roese continue;
55729b103c7SStefan Roese
55829b103c7SStefan Roese /*
55929b103c7SStefan Roese * 8) Activate the RX High Impedance Mode field
56029b103c7SStefan Roese * (bit [2]) in register /PCIe_USB Control (Each MAC
56129b103c7SStefan Roese * contain different Access to reach its
56229b103c7SStefan Roese * Serdes-Regfile).
56329b103c7SStefan Roese * [PEX-Only] Set bit[12]: The analog part latches idle
56429b103c7SStefan Roese * if PU_TX = 1 and PU_PLL =1.
56529b103c7SStefan Roese */
56629b103c7SStefan Roese
56729b103c7SStefan Roese /* Termination enable */
56829b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
56929b103c7SStefan Roese in_direct = (0x48 << 16) | (pex_line_num << 24) |
57029b103c7SStefan Roese 0x1000 | rx_high_imp_mode; /* x1 */
57129b103c7SStefan Roese } else if ((info->pex_mode[pex_unit] ==
57229b103c7SStefan Roese PEX_BUS_MODE_X4) && (pex_line_num == 0))
57329b103c7SStefan Roese in_direct = (0x48 << 16) | (pex_line_num << 24) |
57429b103c7SStefan Roese 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
57529b103c7SStefan Roese else
57629b103c7SStefan Roese in_direct = 0;
57729b103c7SStefan Roese
57829b103c7SStefan Roese if (in_direct) {
57929b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
58029b103c7SStefan Roese in_direct);
58129b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
58229b103c7SStefan Roese in_direct);
58329b103c7SStefan Roese }
58429b103c7SStefan Roese
58529b103c7SStefan Roese continue;
58629b103c7SStefan Roese }
58729b103c7SStefan Roese
58829b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
58929b103c7SStefan Roese /*
59029b103c7SStefan Roese * port 0 for serdes lines 4,6, and port 1 for
59129b103c7SStefan Roese * serdes lines 5
59229b103c7SStefan Roese */
59329b103c7SStefan Roese sata_port = line_num & 1;
59429b103c7SStefan Roese DEBUG_INIT_FULL_S(" - SATA port ");
59529b103c7SStefan Roese DEBUG_INIT_FULL_D_10(sata_port, 2);
59629b103c7SStefan Roese DEBUG_INIT_FULL_S("\n");
59729b103c7SStefan Roese reg_write(SATA_COMPHY_CTRL_REG(sata_port),
59829b103c7SStefan Roese rx_high_imp_mode);
59929b103c7SStefan Roese DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
60029b103c7SStefan Roese rx_high_imp_mode);
60129b103c7SStefan Roese continue;
60229b103c7SStefan Roese }
60329b103c7SStefan Roese
60429b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
60529b103c7SStefan Roese DEBUG_INIT_FULL_S(" - QSGMII\n");
60629b103c7SStefan Roese reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
60729b103c7SStefan Roese DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
60829b103c7SStefan Roese rx_high_imp_mode);
60929b103c7SStefan Roese continue;
61029b103c7SStefan Roese }
61129b103c7SStefan Roese
61229b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
61329b103c7SStefan Roese sgmii_port = 0;
61429b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
61529b103c7SStefan Roese sgmii_port = 1;
61629b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
61729b103c7SStefan Roese sgmii_port = 2;
61829b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
61929b103c7SStefan Roese sgmii_port = 3;
62029b103c7SStefan Roese else
62129b103c7SStefan Roese continue;
62229b103c7SStefan Roese DEBUG_INIT_FULL_S(" - SGMII port ");
62329b103c7SStefan Roese DEBUG_INIT_FULL_D_10(sgmii_port, 2);
62429b103c7SStefan Roese DEBUG_INIT_FULL_S("\n");
62529b103c7SStefan Roese reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
62629b103c7SStefan Roese DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
62729b103c7SStefan Roese rx_high_imp_mode);
62829b103c7SStefan Roese } /* for each serdes lane */
62929b103c7SStefan Roese
63029b103c7SStefan Roese /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
63129b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
63229b103c7SStefan Roese tmp = reg_read(SOC_CTRL_REG);
63329b103c7SStefan Roese DEBUG_RD_REG(SOC_CTRL_REG, tmp);
63429b103c7SStefan Roese tmp &= 0x200;
63529b103c7SStefan Roese if (info->pex_mode[0] == PEX_BUS_MODE_X1)
63629b103c7SStefan Roese tmp |= PCIE0_QUADX1_EN;
63729b103c7SStefan Roese if (info->pex_mode[1] == PEX_BUS_MODE_X1)
63829b103c7SStefan Roese tmp |= PCIE1_QUADX1_EN;
63929b103c7SStefan Roese if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
64029b103c7SStefan Roese PEX_CLK_100MHZ_OFFSET) == 0x1)
64129b103c7SStefan Roese tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
64229b103c7SStefan Roese
64329b103c7SStefan Roese reg_write(SOC_CTRL_REG, tmp);
64429b103c7SStefan Roese DEBUG_WR_REG(SOC_CTRL_REG, tmp);
64529b103c7SStefan Roese
64629b103c7SStefan Roese /* 6.2 PCI Express Link Capabilities */
64729b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
64829b103c7SStefan Roese
64929b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
65029b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
65129b103c7SStefan Roese
65229b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
65329b103c7SStefan Roese /*
65429b103c7SStefan Roese * PCI Express Control
65529b103c7SStefan Roese * 0xX1A00 [0]:
65629b103c7SStefan Roese * 0x0 X4-Link.
65729b103c7SStefan Roese * 0x1 X1-Link
65829b103c7SStefan Roese */
65929b103c7SStefan Roese pex_unit = line_num >> 2;
66029b103c7SStefan Roese pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
66129b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
66229b103c7SStefan Roese continue;
66329b103c7SStefan Roese
66429b103c7SStefan Roese /* set Common Clock Configuration */
66529b103c7SStefan Roese tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
66629b103c7SStefan Roese DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
66729b103c7SStefan Roese tmp |= (1 << 6);
66829b103c7SStefan Roese reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
66929b103c7SStefan Roese DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
67029b103c7SStefan Roese
67129b103c7SStefan Roese tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
67229b103c7SStefan Roese DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
67329b103c7SStefan Roese tmp &= ~(0x3FF);
67429b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
67529b103c7SStefan Roese tmp |= (0x1 << 4);
67629b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
67729b103c7SStefan Roese tmp |= (0x4 << 4);
67829b103c7SStefan Roese if (0 == PEX_CAPABILITY_GET(satr11))
67929b103c7SStefan Roese tmp |= 0x1;
68029b103c7SStefan Roese else
68129b103c7SStefan Roese tmp |= 0x2;
68229b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 6.2: PEX ");
68329b103c7SStefan Roese DEBUG_INIT_FULL_D(pex_if, 1);
68429b103c7SStefan Roese DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
68529b103c7SStefan Roese reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
68629b103c7SStefan Roese DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
68729b103c7SStefan Roese
68829b103c7SStefan Roese /*
68929b103c7SStefan Roese * If pex is X4, no need to pass thru the other
69029b103c7SStefan Roese * 3X1 serdes lines
69129b103c7SStefan Roese */
69229b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
69329b103c7SStefan Roese line_num += 3;
69429b103c7SStefan Roese }
69529b103c7SStefan Roese }
69629b103c7SStefan Roese
69729b103c7SStefan Roese /*
69829b103c7SStefan Roese * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
69929b103c7SStefan Roese * need to config the register SOC_Misc/General Purpose2
70029b103c7SStefan Roese * (Address= 182F8)
70129b103c7SStefan Roese */
70229b103c7SStefan Roese DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
70329b103c7SStefan Roese tmp = reg_read(GEN_PURP_RES_2_REG);
70429b103c7SStefan Roese DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
70529b103c7SStefan Roese
70629b103c7SStefan Roese tmp &= 0xFFFF0000;
70729b103c7SStefan Roese if (info->pex_mode[0] == PEX_BUS_MODE_X4)
70829b103c7SStefan Roese tmp |= 0x0000000F;
70929b103c7SStefan Roese
71029b103c7SStefan Roese if (info->pex_mode[1] == PEX_BUS_MODE_X4)
71129b103c7SStefan Roese tmp |= 0x000000F0;
71229b103c7SStefan Roese
71329b103c7SStefan Roese if (info->pex_mode[2] == PEX_BUS_MODE_X4)
71429b103c7SStefan Roese tmp |= 0x00000F00;
71529b103c7SStefan Roese
71629b103c7SStefan Roese if (info->pex_mode[3] == PEX_BUS_MODE_X4)
71729b103c7SStefan Roese tmp |= 0x0000F000;
71829b103c7SStefan Roese
71929b103c7SStefan Roese reg_write(GEN_PURP_RES_2_REG, tmp);
72029b103c7SStefan Roese DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
72129b103c7SStefan Roese
72229b103c7SStefan Roese /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
72329b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
72429b103c7SStefan Roese
72529b103c7SStefan Roese /* Prepare PHY parameters for each step according to MUX selection */
72629b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
72729b103c7SStefan Roese /* for each serdes lane */
72829b103c7SStefan Roese
72929b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
73029b103c7SStefan Roese
73129b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
73229b103c7SStefan Roese continue;
73329b103c7SStefan Roese
73429b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
73529b103c7SStefan Roese pex_unit = line_num >> 2;
73629b103c7SStefan Roese pex_line_num = line_num % 4;
73729b103c7SStefan Roese
73829b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
73929b103c7SStefan Roese continue;
74029b103c7SStefan Roese /*
74129b103c7SStefan Roese * 8) Configure the desire PHY_MODE (bits [7:5])
74229b103c7SStefan Roese * and REF_FREF_SEL (bits[4:0]) in the register Power
74329b103c7SStefan Roese * and PLL Control (Each MAC contain different Access
74429b103c7SStefan Roese * to reach its Serdes-Regfile).
74529b103c7SStefan Roese */
74629b103c7SStefan Roese if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
74729b103c7SStefan Roese (0 == pex_line_num))
74829b103c7SStefan Roese || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
74929b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
75029b103c7SStefan Roese (0x01 << 16) | (pex_line_num << 24) |
75129b103c7SStefan Roese 0xFC60);
75229b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
75329b103c7SStefan Roese (0x01 << 16) | (pex_line_num << 24)
75429b103c7SStefan Roese | 0xFC60);
75529b103c7SStefan Roese /*
75629b103c7SStefan Roese * Step 8.1: [PEX-Only] Configure Max PLL Rate
75729b103c7SStefan Roese * (bit 8 in KVCO Calibration Control and
75829b103c7SStefan Roese * bits[10:9] in
75929b103c7SStefan Roese */
76029b103c7SStefan Roese /* Use Maximum PLL Rate(Bit 8) */
76129b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
76229b103c7SStefan Roese (0x02 << 16) | (1 << 31) |
76329b103c7SStefan Roese (pex_line_num << 24)); /* read command */
76429b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
76529b103c7SStefan Roese (0x02 << 16) | (1 << 31) |
76629b103c7SStefan Roese (pex_line_num << 24));
76729b103c7SStefan Roese tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
76829b103c7SStefan Roese DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
76929b103c7SStefan Roese tmp &= ~(1 << 31);
77029b103c7SStefan Roese tmp |= (1 << 8);
77129b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
77229b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
77329b103c7SStefan Roese
77429b103c7SStefan Roese /* Use Maximum PLL Rate(Bits [10:9]) */
77529b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
77629b103c7SStefan Roese (0x81 << 16) | (1 << 31) |
77729b103c7SStefan Roese (pex_line_num << 24)); /* read command */
77829b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
77929b103c7SStefan Roese (0x81 << 16) | (1 << 31) |
78029b103c7SStefan Roese (pex_line_num << 24));
78129b103c7SStefan Roese tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
78229b103c7SStefan Roese DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
78329b103c7SStefan Roese tmp &= ~(1 << 31);
78429b103c7SStefan Roese tmp |= (3 << 9);
78529b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
78629b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
78729b103c7SStefan Roese }
78829b103c7SStefan Roese
78929b103c7SStefan Roese continue;
79029b103c7SStefan Roese }
79129b103c7SStefan Roese
79229b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
79329b103c7SStefan Roese /*
79429b103c7SStefan Roese * Port 0 for serdes lines 4,6, and port 1 for serdes
79529b103c7SStefan Roese * lines 5
79629b103c7SStefan Roese */
79729b103c7SStefan Roese sata_port = line_num & 1;
79829b103c7SStefan Roese
79929b103c7SStefan Roese /*
80029b103c7SStefan Roese * 8) Configure the desire PHY_MODE (bits [7:5]) and
80129b103c7SStefan Roese * REF_FREF_SEL (bits[4:0]) in the register Power
80229b103c7SStefan Roese * and PLL Control (Each MAC contain different Access
80329b103c7SStefan Roese * to reach its Serdes-Regfile).
80429b103c7SStefan Roese */
80529b103c7SStefan Roese reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
80629b103c7SStefan Roese DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
80729b103c7SStefan Roese
80829b103c7SStefan Roese /* 9) Configure the desire SEL_BITS */
80929b103c7SStefan Roese reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
81029b103c7SStefan Roese DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
81129b103c7SStefan Roese
81229b103c7SStefan Roese /* 10) Configure the desire REFCLK_SEL */
81329b103c7SStefan Roese
81429b103c7SStefan Roese reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
81529b103c7SStefan Roese DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
81629b103c7SStefan Roese
81729b103c7SStefan Roese /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
81829b103c7SStefan Roese tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
81929b103c7SStefan Roese DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
82029b103c7SStefan Roese tmp |= 7;
82129b103c7SStefan Roese reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
82229b103c7SStefan Roese DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
82329b103c7SStefan Roese
82429b103c7SStefan Roese continue;
82529b103c7SStefan Roese }
82629b103c7SStefan Roese
82729b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
82829b103c7SStefan Roese /*
82929b103c7SStefan Roese * 8) Configure the desire PHY_MODE (bits [7:5])
83029b103c7SStefan Roese * and REF_FREF_SEL (bits[4:0]) in the register
83129b103c7SStefan Roese */
83229b103c7SStefan Roese reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
83329b103c7SStefan Roese DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
83429b103c7SStefan Roese
83529b103c7SStefan Roese /*
83629b103c7SStefan Roese * 9) Configure the desire SEL_BITS (bits [11:0]
83729b103c7SStefan Roese * in register
83829b103c7SStefan Roese */
83929b103c7SStefan Roese reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
84029b103c7SStefan Roese DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
84129b103c7SStefan Roese
84229b103c7SStefan Roese /*
84329b103c7SStefan Roese * 10) Configure the desire REFCLK_SEL (bit [10])
84429b103c7SStefan Roese * in register
84529b103c7SStefan Roese */
84629b103c7SStefan Roese reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
84729b103c7SStefan Roese DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
84829b103c7SStefan Roese
84929b103c7SStefan Roese /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
85029b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_CFG_REG(0));
85129b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
85229b103c7SStefan Roese tmp |= 7;
85329b103c7SStefan Roese reg_write(SGMII_SERDES_CFG_REG(0), tmp);
85429b103c7SStefan Roese DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
85529b103c7SStefan Roese continue;
85629b103c7SStefan Roese }
85729b103c7SStefan Roese
85829b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
85929b103c7SStefan Roese sgmii_port = 0;
86029b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
86129b103c7SStefan Roese sgmii_port = 1;
86229b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
86329b103c7SStefan Roese sgmii_port = 2;
86429b103c7SStefan Roese else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
86529b103c7SStefan Roese sgmii_port = 3;
86629b103c7SStefan Roese else
86729b103c7SStefan Roese continue;
86829b103c7SStefan Roese
86929b103c7SStefan Roese /*
87029b103c7SStefan Roese * 8) Configure the desire PHY_MODE (bits [7:5]) and
87129b103c7SStefan Roese * REF_FREF_SEL (bits[4:0]) in the register
87229b103c7SStefan Roese */
87329b103c7SStefan Roese reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
87429b103c7SStefan Roese DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
87529b103c7SStefan Roese
87629b103c7SStefan Roese /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
87729b103c7SStefan Roese reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
87829b103c7SStefan Roese DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
87929b103c7SStefan Roese
88029b103c7SStefan Roese /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
88129b103c7SStefan Roese reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
88229b103c7SStefan Roese DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
88329b103c7SStefan Roese
88429b103c7SStefan Roese /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
88529b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
88629b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
88729b103c7SStefan Roese tmp |= 7;
88829b103c7SStefan Roese reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
88929b103c7SStefan Roese DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
89029b103c7SStefan Roese
89129b103c7SStefan Roese } /* for each serdes lane */
89229b103c7SStefan Roese
89329b103c7SStefan Roese /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
89429b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
89529b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
89629b103c7SStefan Roese /* for each serdes lane */
89729b103c7SStefan Roese
89829b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
89929b103c7SStefan Roese
90029b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
90129b103c7SStefan Roese continue;
90229b103c7SStefan Roese
90329b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
90429b103c7SStefan Roese pex_unit = line_num >> 2;
90529b103c7SStefan Roese pex_line_num = line_num % 4;
90629b103c7SStefan Roese if (0 == pex_line_num) {
9072399e401SStefan Roese /*
9082399e401SStefan Roese * Configure the detection pulse with before
9092399e401SStefan Roese * the reset is deasserted
9102399e401SStefan Roese */
9112399e401SStefan Roese
9122399e401SStefan Roese /* Read the old value (indirect access) */
9132399e401SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
9142399e401SStefan Roese (0x48 << 16) | (1 << 31) |
9152399e401SStefan Roese (pex_line_num << 24));
9162399e401SStefan Roese tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
9172399e401SStefan Roese tmp &= ~(1 << 31); /* Clear read */
9182399e401SStefan Roese tmp &= ~(3 << 6); /* Mask width */
9192399e401SStefan Roese /* Insert new detection pulse width */
9202399e401SStefan Roese tmp |= serdes_pex_pulse_width[pex_unit] << 6;
9212399e401SStefan Roese /* Write value back */
9222399e401SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
9232399e401SStefan Roese
92429b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG(pex_unit),
92529b103c7SStefan Roese (0xC1 << 16) | 0x24);
92629b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
92729b103c7SStefan Roese (0xC1 << 16) | 0x24);
92829b103c7SStefan Roese }
92929b103c7SStefan Roese }
93029b103c7SStefan Roese }
93129b103c7SStefan Roese
93229b103c7SStefan Roese /*--------------------------------------------------------------*/
93329b103c7SStefan Roese /* Step 13: Wait 15ms before checking results */
93429b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
93529b103c7SStefan Roese mdelay(15);
93629b103c7SStefan Roese tmp = 20;
93729b103c7SStefan Roese while (tmp) {
93829b103c7SStefan Roese status = MV_OK;
93929b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
94029b103c7SStefan Roese u32 tmp;
94129b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
94229b103c7SStefan Roese if (line_cfg ==
94329b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
94429b103c7SStefan Roese continue;
94529b103c7SStefan Roese
94629b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
94729b103c7SStefan Roese continue;
94829b103c7SStefan Roese
94929b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
95029b103c7SStefan Roese /*
95129b103c7SStefan Roese * Port 0 for serdes lines 4,6, and port 1
95229b103c7SStefan Roese * for serdes lines 5
95329b103c7SStefan Roese */
95429b103c7SStefan Roese sata_port = line_num & 1;
95529b103c7SStefan Roese
95629b103c7SStefan Roese tmp =
95729b103c7SStefan Roese reg_read(SATA_LP_PHY_EXT_STAT_REG
95829b103c7SStefan Roese (sata_port));
95929b103c7SStefan Roese DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
96029b103c7SStefan Roese (sata_port), tmp);
96129b103c7SStefan Roese if ((tmp & 0x7) != 0x7)
96229b103c7SStefan Roese status = MV_ERROR;
96329b103c7SStefan Roese continue;
96429b103c7SStefan Roese }
96529b103c7SStefan Roese
96629b103c7SStefan Roese if (line_cfg ==
96729b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
96829b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_STAT_REG(0));
96929b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
97029b103c7SStefan Roese if ((tmp & 0x7) != 0x7)
97129b103c7SStefan Roese status = MV_ERROR;
97229b103c7SStefan Roese continue;
97329b103c7SStefan Roese }
97429b103c7SStefan Roese
97529b103c7SStefan Roese if (line_cfg ==
97629b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_SGMII0])
97729b103c7SStefan Roese sgmii_port = 0;
97829b103c7SStefan Roese else if (line_cfg ==
97929b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_SGMII1])
98029b103c7SStefan Roese sgmii_port = 1;
98129b103c7SStefan Roese else if (line_cfg ==
98229b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_SGMII2])
98329b103c7SStefan Roese sgmii_port = 2;
98429b103c7SStefan Roese else if (line_cfg ==
98529b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_SGMII3])
98629b103c7SStefan Roese sgmii_port = 3;
98729b103c7SStefan Roese else
98829b103c7SStefan Roese continue;
98929b103c7SStefan Roese
99029b103c7SStefan Roese tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
99129b103c7SStefan Roese DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
99229b103c7SStefan Roese if ((tmp & 0x7) != 0x7)
99329b103c7SStefan Roese status = MV_ERROR;
99429b103c7SStefan Roese }
99529b103c7SStefan Roese
99629b103c7SStefan Roese if (status == MV_OK)
99729b103c7SStefan Roese break;
99829b103c7SStefan Roese mdelay(5);
99929b103c7SStefan Roese tmp--;
100029b103c7SStefan Roese }
100129b103c7SStefan Roese
100229b103c7SStefan Roese /*
100329b103c7SStefan Roese * Step14 [PEX-Only] In order to configure RC/EP mode please write
100429b103c7SStefan Roese * to register 0x0060 bits
100529b103c7SStefan Roese */
100629b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
100729b103c7SStefan Roese for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
100829b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
100929b103c7SStefan Roese continue;
101029b103c7SStefan Roese tmp =
101129b103c7SStefan Roese reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
101229b103c7SStefan Roese DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
101329b103c7SStefan Roese tmp);
101429b103c7SStefan Roese tmp &= ~(0xf << 20);
101529b103c7SStefan Roese if (info->pex_type == MV_PEX_ROOT_COMPLEX)
101629b103c7SStefan Roese tmp |= (0x4 << 20);
101729b103c7SStefan Roese else
101829b103c7SStefan Roese tmp |= (0x1 << 20);
101929b103c7SStefan Roese reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
102029b103c7SStefan Roese tmp);
102129b103c7SStefan Roese DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
102229b103c7SStefan Roese tmp);
102329b103c7SStefan Roese }
102429b103c7SStefan Roese
102529b103c7SStefan Roese /*
102629b103c7SStefan Roese * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
102729b103c7SStefan Roese * register 0x1a60
102829b103c7SStefan Roese */
102929b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
103029b103c7SStefan Roese for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
103129b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
103229b103c7SStefan Roese continue;
103329b103c7SStefan Roese if (info->pex_type == MV_PEX_END_POINT) {
103429b103c7SStefan Roese tmp =
103529b103c7SStefan Roese reg_read(PEX_DBG_CTRL_REG
103629b103c7SStefan Roese (MV_PEX_UNIT_TO_IF(pex_unit)));
103729b103c7SStefan Roese DEBUG_RD_REG(PEX_DBG_CTRL_REG
103829b103c7SStefan Roese (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
103929b103c7SStefan Roese tmp &= 0xfff6ffff;
104029b103c7SStefan Roese reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
104129b103c7SStefan Roese tmp);
104229b103c7SStefan Roese DEBUG_WR_REG(PEX_DBG_CTRL_REG
104329b103c7SStefan Roese (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
104429b103c7SStefan Roese }
104529b103c7SStefan Roese }
104629b103c7SStefan Roese
104729b103c7SStefan Roese if (info->serdes_m_phy_change) {
104829b103c7SStefan Roese MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
104929b103c7SStefan Roese u32 bus_speed;
105029b103c7SStefan Roese for (line_num = 0; line_num < max_serdes_lines; line_num++) {
105129b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
105229b103c7SStefan Roese if (line_cfg ==
105329b103c7SStefan Roese serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
105429b103c7SStefan Roese continue;
105529b103c7SStefan Roese serdes_m_phy_change = info->serdes_m_phy_change;
105629b103c7SStefan Roese bus_speed = info->bus_speed & (1 << line_num);
105729b103c7SStefan Roese while (serdes_m_phy_change->type !=
105829b103c7SStefan Roese SERDES_UNIT_UNCONNECTED) {
105929b103c7SStefan Roese switch (serdes_m_phy_change->type) {
106029b103c7SStefan Roese case SERDES_UNIT_PEX:
106129b103c7SStefan Roese if (line_cfg != SERDES_UNIT_PEX)
106229b103c7SStefan Roese break;
106329b103c7SStefan Roese pex_unit = line_num >> 2;
106429b103c7SStefan Roese pex_line_num = line_num % 4;
106529b103c7SStefan Roese if (info->pex_mode[pex_unit] ==
106629b103c7SStefan Roese PEX_BUS_DISABLED)
106729b103c7SStefan Roese break;
106829b103c7SStefan Roese if ((info->pex_mode[pex_unit] ==
106929b103c7SStefan Roese PEX_BUS_MODE_X4) && pex_line_num)
107029b103c7SStefan Roese break;
107129b103c7SStefan Roese
107229b103c7SStefan Roese if (bus_speed) {
107329b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG
107429b103c7SStefan Roese (pex_unit),
107529b103c7SStefan Roese (pex_line_num << 24) |
107629b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
107729b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG
107829b103c7SStefan Roese (pex_unit),
107929b103c7SStefan Roese (pex_line_num <<
108029b103c7SStefan Roese 24) |
108129b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
108229b103c7SStefan Roese } else {
108329b103c7SStefan Roese reg_write(PEX_PHY_ACCESS_REG
108429b103c7SStefan Roese (pex_unit),
108529b103c7SStefan Roese (pex_line_num << 24) |
108629b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
108729b103c7SStefan Roese DEBUG_WR_REG(PEX_PHY_ACCESS_REG
108829b103c7SStefan Roese (pex_unit),
108929b103c7SStefan Roese (pex_line_num <<
109029b103c7SStefan Roese 24) |
109129b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
109229b103c7SStefan Roese }
109329b103c7SStefan Roese break;
109429b103c7SStefan Roese case SERDES_UNIT_SATA:
109529b103c7SStefan Roese if (line_cfg != SERDES_UNIT_SATA)
109629b103c7SStefan Roese break;
109729b103c7SStefan Roese /*
109829b103c7SStefan Roese * Port 0 for serdes lines 4,6, and
109929b103c7SStefan Roese * port 1 for serdes lines 5
110029b103c7SStefan Roese */
110129b103c7SStefan Roese sata_port = line_num & 1;
110229b103c7SStefan Roese if (bus_speed) {
110329b103c7SStefan Roese reg_write(SATA_BASE_REG
110429b103c7SStefan Roese (sata_port) |
110529b103c7SStefan Roese serdes_m_phy_change->reg_hi_speed,
110629b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
110729b103c7SStefan Roese DEBUG_WR_REG(SATA_BASE_REG
110829b103c7SStefan Roese (sata_port) |
110929b103c7SStefan Roese serdes_m_phy_change->reg_hi_speed,
111029b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
111129b103c7SStefan Roese } else {
111229b103c7SStefan Roese reg_write(SATA_BASE_REG
111329b103c7SStefan Roese (sata_port) |
111429b103c7SStefan Roese serdes_m_phy_change->reg_low_speed,
111529b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
111629b103c7SStefan Roese DEBUG_WR_REG(SATA_BASE_REG
111729b103c7SStefan Roese (sata_port) |
111829b103c7SStefan Roese serdes_m_phy_change->reg_low_speed,
111929b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
112029b103c7SStefan Roese }
112129b103c7SStefan Roese break;
112229b103c7SStefan Roese case SERDES_UNIT_SGMII0:
112329b103c7SStefan Roese case SERDES_UNIT_SGMII1:
112429b103c7SStefan Roese case SERDES_UNIT_SGMII2:
112529b103c7SStefan Roese case SERDES_UNIT_SGMII3:
112629b103c7SStefan Roese if (line_cfg == serdes_cfg[line_num]
112729b103c7SStefan Roese [SERDES_UNIT_SGMII0])
112829b103c7SStefan Roese sgmii_port = 0;
112929b103c7SStefan Roese else if (line_cfg ==
113029b103c7SStefan Roese serdes_cfg[line_num]
113129b103c7SStefan Roese [SERDES_UNIT_SGMII1])
113229b103c7SStefan Roese sgmii_port = 1;
113329b103c7SStefan Roese else if (line_cfg ==
113429b103c7SStefan Roese serdes_cfg[line_num]
113529b103c7SStefan Roese [SERDES_UNIT_SGMII2])
113629b103c7SStefan Roese sgmii_port = 2;
113729b103c7SStefan Roese else if (line_cfg ==
113829b103c7SStefan Roese serdes_cfg[line_num]
113929b103c7SStefan Roese [SERDES_UNIT_SGMII3])
114029b103c7SStefan Roese sgmii_port = 3;
114129b103c7SStefan Roese else
114229b103c7SStefan Roese break;
114329b103c7SStefan Roese if (bus_speed) {
114429b103c7SStefan Roese reg_write(MV_ETH_REGS_BASE
114529b103c7SStefan Roese (sgmii_port) |
114629b103c7SStefan Roese serdes_m_phy_change->reg_hi_speed,
114729b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
114829b103c7SStefan Roese DEBUG_WR_REG(MV_ETH_REGS_BASE
114929b103c7SStefan Roese (sgmii_port) |
115029b103c7SStefan Roese serdes_m_phy_change->reg_hi_speed,
115129b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
115229b103c7SStefan Roese } else {
115329b103c7SStefan Roese reg_write(MV_ETH_REGS_BASE
115429b103c7SStefan Roese (sgmii_port) |
115529b103c7SStefan Roese serdes_m_phy_change->reg_low_speed,
115629b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
115729b103c7SStefan Roese DEBUG_WR_REG(MV_ETH_REGS_BASE
115829b103c7SStefan Roese (sgmii_port) |
115929b103c7SStefan Roese serdes_m_phy_change->reg_low_speed,
116029b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
116129b103c7SStefan Roese }
116229b103c7SStefan Roese break;
116329b103c7SStefan Roese case SERDES_UNIT_QSGMII:
116429b103c7SStefan Roese if (line_cfg != SERDES_UNIT_QSGMII)
116529b103c7SStefan Roese break;
116629b103c7SStefan Roese if (bus_speed) {
116729b103c7SStefan Roese reg_write
116829b103c7SStefan Roese (serdes_m_phy_change->reg_hi_speed,
116929b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
117029b103c7SStefan Roese DEBUG_WR_REG
117129b103c7SStefan Roese (serdes_m_phy_change->reg_hi_speed,
117229b103c7SStefan Roese serdes_m_phy_change->val_hi_speed);
117329b103c7SStefan Roese } else {
117429b103c7SStefan Roese reg_write
117529b103c7SStefan Roese (serdes_m_phy_change->reg_low_speed,
117629b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
117729b103c7SStefan Roese DEBUG_WR_REG
117829b103c7SStefan Roese (serdes_m_phy_change->reg_low_speed,
117929b103c7SStefan Roese serdes_m_phy_change->val_low_speed);
118029b103c7SStefan Roese }
118129b103c7SStefan Roese break;
118229b103c7SStefan Roese default:
118329b103c7SStefan Roese break;
118429b103c7SStefan Roese }
118529b103c7SStefan Roese serdes_m_phy_change++;
118629b103c7SStefan Roese }
118729b103c7SStefan Roese }
118829b103c7SStefan Roese }
118929b103c7SStefan Roese
119029b103c7SStefan Roese /* Step 16 [PEX-Only] Training Enable */
119129b103c7SStefan Roese DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
119229b103c7SStefan Roese tmp = reg_read(SOC_CTRL_REG);
119329b103c7SStefan Roese DEBUG_RD_REG(SOC_CTRL_REG, tmp);
119429b103c7SStefan Roese tmp &= ~(0x0F);
119529b103c7SStefan Roese for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
119629b103c7SStefan Roese reg_write(PEX_CAUSE_REG(pex_unit), 0);
119729b103c7SStefan Roese DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
119829b103c7SStefan Roese if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
119929b103c7SStefan Roese tmp |= (0x1 << pex_unit);
120029b103c7SStefan Roese }
120129b103c7SStefan Roese reg_write(SOC_CTRL_REG, tmp);
120229b103c7SStefan Roese DEBUG_WR_REG(SOC_CTRL_REG, tmp);
120329b103c7SStefan Roese
120429b103c7SStefan Roese /* Step 17: Speed change to target speed and width */
120529b103c7SStefan Roese {
120629b103c7SStefan Roese u32 tmp_reg, tmp_pex_reg;
120729b103c7SStefan Roese u32 addr;
120829b103c7SStefan Roese u32 first_busno, next_busno;
120929b103c7SStefan Roese u32 max_link_width = 0;
121029b103c7SStefan Roese u32 neg_link_width = 0;
121129b103c7SStefan Roese pex_if_num = pex_max_if_get();
121229b103c7SStefan Roese mdelay(150);
121329b103c7SStefan Roese DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
121429b103c7SStefan Roese next_busno = 0;
121529b103c7SStefan Roese for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
121629b103c7SStefan Roese line_num = (pex_if <= 8) ? pex_if : 12;
121729b103c7SStefan Roese line_cfg = get_line_cfg(line_num, info);
121829b103c7SStefan Roese if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
121929b103c7SStefan Roese continue;
122029b103c7SStefan Roese pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
122129b103c7SStefan Roese DEBUG_INIT_FULL_S("step 17: PEX");
122229b103c7SStefan Roese DEBUG_INIT_FULL_D(pex_if, 1);
122329b103c7SStefan Roese DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
122429b103c7SStefan Roese
122529b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
122629b103c7SStefan Roese DEBUG_INIT_FULL_C("PEX disabled interface ",
122729b103c7SStefan Roese pex_if, 1);
122829b103c7SStefan Roese if (pex_if < 8)
122929b103c7SStefan Roese pex_if += 3;
123029b103c7SStefan Roese continue;
123129b103c7SStefan Roese }
123229b103c7SStefan Roese first_busno = next_busno;
123329b103c7SStefan Roese if ((info->pex_type == MV_PEX_END_POINT) &&
123429b103c7SStefan Roese (0 == pex_if)) {
123529b103c7SStefan Roese if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
123629b103c7SStefan Roese PEX_BUS_MODE_X4))
123729b103c7SStefan Roese pex_if += 3;
123829b103c7SStefan Roese continue;
123929b103c7SStefan Roese }
124029b103c7SStefan Roese
124129b103c7SStefan Roese tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
124229b103c7SStefan Roese DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
124329b103c7SStefan Roese if ((tmp & 0x7f) == 0x7e) {
124429b103c7SStefan Roese next_busno++;
124529b103c7SStefan Roese tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
124629b103c7SStefan Roese max_link_width = tmp;
124729b103c7SStefan Roese DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
124829b103c7SStefan Roese (pex_if)), tmp);
124929b103c7SStefan Roese max_link_width = ((max_link_width >> 4) & 0x3F);
125029b103c7SStefan Roese neg_link_width =
125129b103c7SStefan Roese reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
125229b103c7SStefan Roese DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
125329b103c7SStefan Roese neg_link_width);
125429b103c7SStefan Roese neg_link_width = ((neg_link_width >> 20) & 0x3F);
125529b103c7SStefan Roese if (max_link_width > neg_link_width) {
125629b103c7SStefan Roese tmp &= ~(0x3F << 4);
125729b103c7SStefan Roese tmp |= (neg_link_width << 4);
125829b103c7SStefan Roese reg_write(PEX_LINK_CAPABILITIES_REG
125929b103c7SStefan Roese (pex_if), tmp);
126029b103c7SStefan Roese DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
126129b103c7SStefan Roese (pex_if)), tmp);
126229b103c7SStefan Roese mdelay(1); /* wait 1ms before reading capability for speed */
126329b103c7SStefan Roese DEBUG_INIT_S("PEX");
126429b103c7SStefan Roese DEBUG_INIT_D(pex_if, 1);
126529b103c7SStefan Roese DEBUG_INIT_C(": change width to X",
126629b103c7SStefan Roese neg_link_width, 1);
126729b103c7SStefan Roese }
126829b103c7SStefan Roese tmp_pex_reg =
126929b103c7SStefan Roese reg_read((PEX_CFG_DIRECT_ACCESS
127029b103c7SStefan Roese (pex_if,
127129b103c7SStefan Roese PEX_LINK_CAPABILITY_REG)));
127229b103c7SStefan Roese DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
127329b103c7SStefan Roese (pex_if,
127429b103c7SStefan Roese PEX_LINK_CAPABILITY_REG)),
127529b103c7SStefan Roese tmp_pex_reg);
127629b103c7SStefan Roese tmp_pex_reg &= (0xF);
127729b103c7SStefan Roese if (tmp_pex_reg == 0x2) {
127829b103c7SStefan Roese tmp_reg =
127929b103c7SStefan Roese (reg_read
128029b103c7SStefan Roese (PEX_CFG_DIRECT_ACCESS
128129b103c7SStefan Roese (pex_if,
128229b103c7SStefan Roese PEX_LINK_CTRL_STAT_REG)) &
128329b103c7SStefan Roese 0xF0000) >> 16;
128429b103c7SStefan Roese DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
128529b103c7SStefan Roese (pex_if,
128629b103c7SStefan Roese PEX_LINK_CTRL_STAT_REG),
128729b103c7SStefan Roese tmp_pex_reg);
128829b103c7SStefan Roese /* check if the link established is GEN1 */
128929b103c7SStefan Roese if (tmp_reg == 0x1) {
129029b103c7SStefan Roese pex_local_bus_num_set(pex_if,
129129b103c7SStefan Roese first_busno);
129229b103c7SStefan Roese pex_local_dev_num_set(pex_if,
129329b103c7SStefan Roese 1);
129429b103c7SStefan Roese
129529b103c7SStefan Roese DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
129629b103c7SStefan Roese /* link is Gen1, check the EP capability */
129729b103c7SStefan Roese addr =
129829b103c7SStefan Roese pex_cfg_read(pex_if,
129929b103c7SStefan Roese first_busno, 0,
130029b103c7SStefan Roese 0,
130129b103c7SStefan Roese 0x34) & 0xFF;
130229b103c7SStefan Roese DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
130329b103c7SStefan Roese addr, 4);
130429b103c7SStefan Roese if (addr == 0xff) {
130529b103c7SStefan Roese DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
130629b103c7SStefan Roese pex_if, 1);
130729b103c7SStefan Roese continue;
130829b103c7SStefan Roese }
130929b103c7SStefan Roese while ((pex_cfg_read
131029b103c7SStefan Roese (pex_if, first_busno, 0,
131129b103c7SStefan Roese 0,
131229b103c7SStefan Roese addr) & 0xFF) !=
131329b103c7SStefan Roese 0x10) {
131429b103c7SStefan Roese addr =
131529b103c7SStefan Roese (pex_cfg_read
131629b103c7SStefan Roese (pex_if,
131729b103c7SStefan Roese first_busno, 0, 0,
131829b103c7SStefan Roese addr) & 0xFF00) >>
131929b103c7SStefan Roese 8;
132029b103c7SStefan Roese }
132129b103c7SStefan Roese if ((pex_cfg_read
132229b103c7SStefan Roese (pex_if, first_busno, 0, 0,
132329b103c7SStefan Roese addr + 0xC) & 0xF) >=
132429b103c7SStefan Roese 0x2) {
132529b103c7SStefan Roese tmp =
132629b103c7SStefan Roese reg_read
132729b103c7SStefan Roese (PEX_LINK_CTRL_STATUS2_REG
132829b103c7SStefan Roese (pex_if));
132929b103c7SStefan Roese DEBUG_RD_REG
133029b103c7SStefan Roese (PEX_LINK_CTRL_STATUS2_REG
133129b103c7SStefan Roese (pex_if), tmp);
133229b103c7SStefan Roese tmp &= ~(0x1 | 1 << 1);
133329b103c7SStefan Roese tmp |= (1 << 1);
133429b103c7SStefan Roese reg_write
133529b103c7SStefan Roese (PEX_LINK_CTRL_STATUS2_REG
133629b103c7SStefan Roese (pex_if), tmp);
133729b103c7SStefan Roese DEBUG_WR_REG
133829b103c7SStefan Roese (PEX_LINK_CTRL_STATUS2_REG
133929b103c7SStefan Roese (pex_if), tmp);
134029b103c7SStefan Roese
134129b103c7SStefan Roese tmp =
134229b103c7SStefan Roese reg_read
134329b103c7SStefan Roese (PEX_CTRL_REG
134429b103c7SStefan Roese (pex_if));
134529b103c7SStefan Roese DEBUG_RD_REG
134629b103c7SStefan Roese (PEX_CTRL_REG
134729b103c7SStefan Roese (pex_if), tmp);
134829b103c7SStefan Roese tmp |= (1 << 10);
134929b103c7SStefan Roese reg_write(PEX_CTRL_REG
135029b103c7SStefan Roese (pex_if),
135129b103c7SStefan Roese tmp);
135229b103c7SStefan Roese DEBUG_WR_REG
135329b103c7SStefan Roese (PEX_CTRL_REG
135429b103c7SStefan Roese (pex_if), tmp);
135529b103c7SStefan Roese mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
135629b103c7SStefan Roese DEBUG_INIT_FULL_S
135729b103c7SStefan Roese ("Gen2 client!\n");
135829b103c7SStefan Roese } else {
135929b103c7SStefan Roese DEBUG_INIT_FULL_S
136029b103c7SStefan Roese ("GEN1 client!\n");
136129b103c7SStefan Roese }
136229b103c7SStefan Roese }
136329b103c7SStefan Roese }
136429b103c7SStefan Roese } else {
136529b103c7SStefan Roese DEBUG_INIT_FULL_S("PEX");
136629b103c7SStefan Roese DEBUG_INIT_FULL_D(pex_if, 1);
136729b103c7SStefan Roese DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
136829b103c7SStefan Roese DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
136929b103c7SStefan Roese 8);
137029b103c7SStefan Roese DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
137129b103c7SStefan Roese }
137229b103c7SStefan Roese
137329b103c7SStefan Roese if ((pex_if < 8) &&
137429b103c7SStefan Roese (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
137529b103c7SStefan Roese pex_if += 3;
137629b103c7SStefan Roese }
137729b103c7SStefan Roese }
137829b103c7SStefan Roese
137929b103c7SStefan Roese /* Step 18: update pex DEVICE ID */
138029b103c7SStefan Roese {
138129b103c7SStefan Roese u32 devId;
138229b103c7SStefan Roese pex_if_num = pex_max_if_get();
138329b103c7SStefan Roese ctrl_mode = ctrl_model_get();
138429b103c7SStefan Roese for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
138529b103c7SStefan Roese pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
138629b103c7SStefan Roese if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
138729b103c7SStefan Roese if ((pex_if < 8) &&
138829b103c7SStefan Roese (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
138929b103c7SStefan Roese pex_if += 3;
139029b103c7SStefan Roese continue;
139129b103c7SStefan Roese }
139229b103c7SStefan Roese
139329b103c7SStefan Roese devId = reg_read(PEX_CFG_DIRECT_ACCESS(
139429b103c7SStefan Roese pex_if, PEX_DEVICE_AND_VENDOR_ID));
139529b103c7SStefan Roese devId &= 0xFFFF;
139629b103c7SStefan Roese devId |= ((ctrl_mode << 16) & 0xffff0000);
1397e25d5a95SStefan Roese DEBUG_INIT_FULL_S("Update Device ID PEX");
1398e25d5a95SStefan Roese DEBUG_INIT_FULL_D(pex_if, 1);
1399e25d5a95SStefan Roese DEBUG_INIT_FULL_D(devId, 8);
1400e25d5a95SStefan Roese DEBUG_INIT_FULL_S("\n");
140129b103c7SStefan Roese reg_write(PEX_CFG_DIRECT_ACCESS
140229b103c7SStefan Roese (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
140329b103c7SStefan Roese if ((pex_if < 8) &&
140429b103c7SStefan Roese (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
140529b103c7SStefan Roese pex_if += 3;
140629b103c7SStefan Roese }
1407e25d5a95SStefan Roese DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
1408e25d5a95SStefan Roese DEBUG_INIT_FULL_D(ctrl_mode, 4);
1409e25d5a95SStefan Roese DEBUG_INIT_FULL_S("0\n");
141029b103c7SStefan Roese }
141129b103c7SStefan Roese tmp = reg_read(PEX_DBG_STATUS_REG(0));
141229b103c7SStefan Roese DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
141329b103c7SStefan Roese
141429b103c7SStefan Roese DEBUG_INIT_S(ENDED_OK);
141529b103c7SStefan Roese return MV_OK;
141629b103c7SStefan Roese }
141729b103c7SStefan Roese
141829b103c7SStefan Roese /* PEX configuration space read write */
141929b103c7SStefan Roese
142029b103c7SStefan Roese /*
142129b103c7SStefan Roese * pex_cfg_read - Read from configuration space
142229b103c7SStefan Roese *
142329b103c7SStefan Roese * DESCRIPTION:
142429b103c7SStefan Roese * This function performs a 32 bit read from PEX configuration space.
142529b103c7SStefan Roese * It supports both type 0 and type 1 of Configuration Transactions
142629b103c7SStefan Roese * (local and over bridge). In order to read from local bus segment, use
142729b103c7SStefan Roese * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
142829b103c7SStefan Roese * will result configuration transaction of type 1 (over bridge).
142929b103c7SStefan Roese *
143029b103c7SStefan Roese * INPUT:
143129b103c7SStefan Roese * pex_if - PEX interface number.
143229b103c7SStefan Roese * bus - PEX segment bus number.
143329b103c7SStefan Roese * dev - PEX device number.
143429b103c7SStefan Roese * func - Function number.
143529b103c7SStefan Roese * offss - Register offset.
143629b103c7SStefan Roese *
143729b103c7SStefan Roese * OUTPUT:
143829b103c7SStefan Roese * None.
143929b103c7SStefan Roese *
144029b103c7SStefan Roese * RETURN:
144129b103c7SStefan Roese * 32bit register data, 0xffffffff on error
144229b103c7SStefan Roese *
144329b103c7SStefan Roese */
pex_cfg_read(u32 pex_if,u32 bus,u32 dev,u32 func,u32 offs)144429b103c7SStefan Roese u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
144529b103c7SStefan Roese {
144629b103c7SStefan Roese u32 pex_data = 0;
144729b103c7SStefan Roese u32 local_dev, local_bus;
144829b103c7SStefan Roese u32 val;
144929b103c7SStefan Roese
145029b103c7SStefan Roese if (pex_if >= MV_PEX_MAX_IF)
145129b103c7SStefan Roese return 0xFFFFFFFF;
145229b103c7SStefan Roese
145329b103c7SStefan Roese if (dev >= MAX_PEX_DEVICES) {
145429b103c7SStefan Roese DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
145529b103c7SStefan Roese 1);
145629b103c7SStefan Roese return 0xFFFFFFFF;
145729b103c7SStefan Roese }
145829b103c7SStefan Roese
145929b103c7SStefan Roese if (func >= MAX_PEX_FUNCS) {
146029b103c7SStefan Roese DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
146129b103c7SStefan Roese 1);
146229b103c7SStefan Roese return 0xFFFFFFFF;
146329b103c7SStefan Roese }
146429b103c7SStefan Roese
146529b103c7SStefan Roese if (bus >= MAX_PEX_BUSSES) {
146629b103c7SStefan Roese DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
146729b103c7SStefan Roese return MV_ERROR;
146829b103c7SStefan Roese }
146929b103c7SStefan Roese val = reg_read(PEX_STATUS_REG(pex_if));
147029b103c7SStefan Roese
147129b103c7SStefan Roese local_dev =
147229b103c7SStefan Roese ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
147329b103c7SStefan Roese local_bus =
147429b103c7SStefan Roese ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
147529b103c7SStefan Roese
147629b103c7SStefan Roese /* Speed up the process. In case on no link, return MV_ERROR */
147729b103c7SStefan Roese if ((dev != local_dev) || (bus != local_bus)) {
147829b103c7SStefan Roese pex_data = reg_read(PEX_STATUS_REG(pex_if));
147929b103c7SStefan Roese
148029b103c7SStefan Roese if ((pex_data & PXSR_DL_DOWN))
148129b103c7SStefan Roese return MV_ERROR;
148229b103c7SStefan Roese }
148329b103c7SStefan Roese
148429b103c7SStefan Roese /*
148529b103c7SStefan Roese * In PCI Express we have only one device number
148629b103c7SStefan Roese * and this number is the first number we encounter else that the
148729b103c7SStefan Roese * local_dev spec pex define return on config read/write on any device
148829b103c7SStefan Roese */
148929b103c7SStefan Roese if (bus == local_bus) {
149029b103c7SStefan Roese if (local_dev == 0) {
149129b103c7SStefan Roese /*
149229b103c7SStefan Roese * If local dev is 0 then the first number we encounter
149329b103c7SStefan Roese * after 0 is 1
149429b103c7SStefan Roese */
149529b103c7SStefan Roese if ((dev != 1) && (dev != local_dev))
149629b103c7SStefan Roese return MV_ERROR;
149729b103c7SStefan Roese } else {
149829b103c7SStefan Roese /*
149929b103c7SStefan Roese * If local dev is not 0 then the first number we
150029b103c7SStefan Roese * encounter is 0
150129b103c7SStefan Roese */
150229b103c7SStefan Roese if ((dev != 0) && (dev != local_dev))
150329b103c7SStefan Roese return MV_ERROR;
150429b103c7SStefan Roese }
150529b103c7SStefan Roese }
150629b103c7SStefan Roese
150729b103c7SStefan Roese /* Creating PEX address to be passed */
150829b103c7SStefan Roese pex_data = (bus << PXCAR_BUS_NUM_OFFS);
150929b103c7SStefan Roese pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
151029b103c7SStefan Roese pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
151129b103c7SStefan Roese pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
151229b103c7SStefan Roese /* extended register space */
151329b103c7SStefan Roese pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
151429b103c7SStefan Roese PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
151529b103c7SStefan Roese
151629b103c7SStefan Roese pex_data |= PXCAR_CONFIG_EN;
151729b103c7SStefan Roese
151829b103c7SStefan Roese /* Write the address to the PEX configuration address register */
151929b103c7SStefan Roese reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
152029b103c7SStefan Roese
152129b103c7SStefan Roese /*
152229b103c7SStefan Roese * In order to let the PEX controller absorbed the address of the read
152329b103c7SStefan Roese * transaction we perform a validity check that the address was written
152429b103c7SStefan Roese */
152529b103c7SStefan Roese if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
152629b103c7SStefan Roese return MV_ERROR;
152729b103c7SStefan Roese
152829b103c7SStefan Roese /* cleaning Master Abort */
152929b103c7SStefan Roese reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
153029b103c7SStefan Roese PXSAC_MABORT);
153129b103c7SStefan Roese /* Read the Data returned in the PEX Data register */
153229b103c7SStefan Roese pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
153329b103c7SStefan Roese
153429b103c7SStefan Roese DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
153529b103c7SStefan Roese
153629b103c7SStefan Roese return pex_data;
153729b103c7SStefan Roese }
153829b103c7SStefan Roese
153929b103c7SStefan Roese /*
154029b103c7SStefan Roese * pex_local_bus_num_set - Set PEX interface local bus number.
154129b103c7SStefan Roese *
154229b103c7SStefan Roese * DESCRIPTION:
154329b103c7SStefan Roese * This function sets given PEX interface its local bus number.
154429b103c7SStefan Roese * Note: In case the PEX interface is PEX-X, the information is read-only.
154529b103c7SStefan Roese *
154629b103c7SStefan Roese * INPUT:
154729b103c7SStefan Roese * pex_if - PEX interface number.
154829b103c7SStefan Roese * bus_num - Bus number.
154929b103c7SStefan Roese *
155029b103c7SStefan Roese * OUTPUT:
155129b103c7SStefan Roese * None.
155229b103c7SStefan Roese *
155329b103c7SStefan Roese * RETURN:
155429b103c7SStefan Roese * MV_NOT_ALLOWED in case PEX interface is PEX-X.
155529b103c7SStefan Roese * MV_BAD_PARAM on bad parameters ,
155629b103c7SStefan Roese * otherwise MV_OK
155729b103c7SStefan Roese *
155829b103c7SStefan Roese */
pex_local_bus_num_set(u32 pex_if,u32 bus_num)155929b103c7SStefan Roese int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
156029b103c7SStefan Roese {
156129b103c7SStefan Roese u32 val;
156229b103c7SStefan Roese
156329b103c7SStefan Roese if (bus_num >= MAX_PEX_BUSSES) {
156429b103c7SStefan Roese DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
156529b103c7SStefan Roese bus_num, 4);
156629b103c7SStefan Roese return MV_ERROR;
156729b103c7SStefan Roese }
156829b103c7SStefan Roese
156929b103c7SStefan Roese val = reg_read(PEX_STATUS_REG(pex_if));
157029b103c7SStefan Roese val &= ~PXSR_PEX_BUS_NUM_MASK;
157129b103c7SStefan Roese val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
157229b103c7SStefan Roese reg_write(PEX_STATUS_REG(pex_if), val);
157329b103c7SStefan Roese
157429b103c7SStefan Roese return MV_OK;
157529b103c7SStefan Roese }
157629b103c7SStefan Roese
157729b103c7SStefan Roese /*
157829b103c7SStefan Roese * pex_local_dev_num_set - Set PEX interface local device number.
157929b103c7SStefan Roese *
158029b103c7SStefan Roese * DESCRIPTION:
158129b103c7SStefan Roese * This function sets given PEX interface its local device number.
158229b103c7SStefan Roese * Note: In case the PEX interface is PEX-X, the information is read-only.
158329b103c7SStefan Roese *
158429b103c7SStefan Roese * INPUT:
158529b103c7SStefan Roese * pex_if - PEX interface number.
158629b103c7SStefan Roese * dev_num - Device number.
158729b103c7SStefan Roese *
158829b103c7SStefan Roese * OUTPUT:
158929b103c7SStefan Roese * None.
159029b103c7SStefan Roese *
159129b103c7SStefan Roese * RETURN:
159229b103c7SStefan Roese * MV_NOT_ALLOWED in case PEX interface is PEX-X.
159329b103c7SStefan Roese * MV_BAD_PARAM on bad parameters ,
159429b103c7SStefan Roese * otherwise MV_OK
159529b103c7SStefan Roese *
159629b103c7SStefan Roese */
pex_local_dev_num_set(u32 pex_if,u32 dev_num)159729b103c7SStefan Roese int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
159829b103c7SStefan Roese {
159929b103c7SStefan Roese u32 val;
160029b103c7SStefan Roese
160129b103c7SStefan Roese if (pex_if >= MV_PEX_MAX_IF)
160229b103c7SStefan Roese return MV_BAD_PARAM;
160329b103c7SStefan Roese
160429b103c7SStefan Roese val = reg_read(PEX_STATUS_REG(pex_if));
160529b103c7SStefan Roese val &= ~PXSR_PEX_DEV_NUM_MASK;
160629b103c7SStefan Roese val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
160729b103c7SStefan Roese reg_write(PEX_STATUS_REG(pex_if), val);
160829b103c7SStefan Roese
160929b103c7SStefan Roese return MV_OK;
161029b103c7SStefan Roese }
1611