1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 229b103c7SStefan Roese /* 329b103c7SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 429b103c7SStefan Roese */ 529b103c7SStefan Roese 629b103c7SStefan Roese #ifndef __BOARD_ENV_SPEC 729b103c7SStefan Roese #define __BOARD_ENV_SPEC 829b103c7SStefan Roese 929b103c7SStefan Roese /* Board specific configuration */ 1029b103c7SStefan Roese 1129b103c7SStefan Roese /* KW40 */ 1229b103c7SStefan Roese #define MV_6710_DEV_ID 0x6710 1329b103c7SStefan Roese 1429b103c7SStefan Roese #define MV_6710_Z1_REV 0x0 1529b103c7SStefan Roese #define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV) 1629b103c7SStefan Roese #define MV_6710_Z1_NAME "MV6710 Z1" 1729b103c7SStefan Roese 1829b103c7SStefan Roese /* Armada XP Family */ 1929b103c7SStefan Roese #define MV_78130_DEV_ID 0x7813 2029b103c7SStefan Roese #define MV_78160_DEV_ID 0x7816 2129b103c7SStefan Roese #define MV_78230_DEV_ID 0x7823 2229b103c7SStefan Roese #define MV_78260_DEV_ID 0x7826 2329b103c7SStefan Roese #define MV_78460_DEV_ID 0x7846 2429b103c7SStefan Roese #define MV_78000_DEV_ID 0x7888 2529b103c7SStefan Roese 2629b103c7SStefan Roese #define MV_FPGA_DEV_ID 0x2107 2729b103c7SStefan Roese 2829b103c7SStefan Roese #define MV_78XX0_Z1_REV 0x0 2929b103c7SStefan Roese 3029b103c7SStefan Roese /* boards ID numbers */ 3129b103c7SStefan Roese #define BOARD_ID_BASE 0x0 3229b103c7SStefan Roese 3329b103c7SStefan Roese /* New board ID numbers */ 3400a457b2SStefan Roese #define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1) 3529b103c7SStefan Roese #define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) 3629b103c7SStefan Roese #define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) 3729b103c7SStefan Roese #define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) 3829b103c7SStefan Roese #define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1) 3929b103c7SStefan Roese #define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1) 4029b103c7SStefan Roese #define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1) 4129b103c7SStefan Roese #define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1) 4229b103c7SStefan Roese #define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1) 4329b103c7SStefan Roese #define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) 4429b103c7SStefan Roese #define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) 4529b103c7SStefan Roese #define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) 46aefb8f4cSPhil Sutter #define INVALID_BOARD_ID 0xFFFFFFFF 4729b103c7SStefan Roese 4829b103c7SStefan Roese /* Sample at Reset */ 4929b103c7SStefan Roese #define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) 5029b103c7SStefan Roese 5129b103c7SStefan Roese /* BIOS Modes related defines */ 5229b103c7SStefan Roese 5329b103c7SStefan Roese #define SAR0_BOOTWIDTH_OFFSET 3 5429b103c7SStefan Roese #define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET) 5529b103c7SStefan Roese #define SAR0_BOOTSRC_OFFSET 5 5629b103c7SStefan Roese #define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET) 5729b103c7SStefan Roese 5829b103c7SStefan Roese #define SAR0_L2_SIZE_OFFSET 19 5929b103c7SStefan Roese #define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET) 6029b103c7SStefan Roese #define SAR0_CPU_FREQ_OFFSET 21 6129b103c7SStefan Roese #define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET) 6229b103c7SStefan Roese #define SAR0_FABRIC_FREQ_OFFSET 24 6329b103c7SStefan Roese #define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET) 6429b103c7SStefan Roese #define SAR0_CPU0CORE_OFFSET 31 6529b103c7SStefan Roese #define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET) 6629b103c7SStefan Roese #define SAR1_CPU0CORE_OFFSET 0 6729b103c7SStefan Roese #define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET) 6829b103c7SStefan Roese 6929b103c7SStefan Roese #define PEX_CLK_100MHZ_OFFSET 2 7029b103c7SStefan Roese #define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET) 7129b103c7SStefan Roese 7229b103c7SStefan Roese #define SAR1_FABRIC_MODE_OFFSET 19 7329b103c7SStefan Roese #define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET) 7429b103c7SStefan Roese #define SAR1_CPU_MODE_OFFSET 20 7529b103c7SStefan Roese #define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET) 7629b103c7SStefan Roese 7729b103c7SStefan Roese #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) 7829b103c7SStefan Roese 7929b103c7SStefan Roese 8029b103c7SStefan Roese #define CORE_AVS_CONTROL_0REG 0x18300 8129b103c7SStefan Roese #define CORE_AVS_CONTROL_2REG 0x18308 8229b103c7SStefan Roese #define CPU_AVS_CONTROL2_REG 0x20868 8329b103c7SStefan Roese #define CPU_AVS_CONTROL0_REG 0x20860 8429b103c7SStefan Roese #define GENERAL_PURPOSE_RESERVED0_REG 0x182E0 8529b103c7SStefan Roese 8629b103c7SStefan Roese #define MSAR_TCLK_OFFS 28 8729b103c7SStefan Roese #define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) 8829b103c7SStefan Roese 8929b103c7SStefan Roese 9029b103c7SStefan Roese /* Controler environment registers offsets */ 9129b103c7SStefan Roese #define GEN_PURP_RES_1_REG 0x182F4 9229b103c7SStefan Roese #define GEN_PURP_RES_2_REG 0x182F8 9329b103c7SStefan Roese 9429b103c7SStefan Roese /* registers offsets */ 9529b103c7SStefan Roese #define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40)) 9629b103c7SStefan Roese #define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 9729b103c7SStefan Roese #define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) 9829b103c7SStefan Roese #define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0) 9929b103c7SStefan Roese 10029b103c7SStefan Roese #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 10129b103c7SStefan Roese #define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */ 10229b103c7SStefan Roese #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 10329b103c7SStefan Roese #define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08) 10429b103c7SStefan Roese #define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C) 10529b103c7SStefan Roese #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 10629b103c7SStefan Roese #define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14) 10729b103c7SStefan Roese #define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18) 10829b103c7SStefan Roese #define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C) 10929b103c7SStefan Roese #define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40)) 11029b103c7SStefan Roese #define GPP_64_66_DATA_OUT_SET_REG 0x181A4 11129b103c7SStefan Roese #define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40)) 11229b103c7SStefan Roese #define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0 11329b103c7SStefan Roese #define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40) 11429b103c7SStefan Roese 11529b103c7SStefan Roese #define MV_GPP66 (1 << 2) 11629b103c7SStefan Roese 11729b103c7SStefan Roese /* Relevant for MV78XX0 */ 11829b103c7SStefan Roese #define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20) 11929b103c7SStefan Roese #define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24) 12029b103c7SStefan Roese 12129b103c7SStefan Roese /* This define describes the maximum number of supported PEX Interfaces */ 12229b103c7SStefan Roese #define MV_PEX_MAX_IF 10 12329b103c7SStefan Roese #define MV_PEX_MAX_UNIT 4 12429b103c7SStefan Roese 12529b103c7SStefan Roese #define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12))) 12629b103c7SStefan Roese 12729b103c7SStefan Roese #define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \ 12829b103c7SStefan Roese ((unit)/2 * 0x2000) + 0x1B00) 12929b103c7SStefan Roese 13029b103c7SStefan Roese #define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000) 13129b103c7SStefan Roese 13229b103c7SStefan Roese #define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804) 13329b103c7SStefan Roese #define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C) 13429b103c7SStefan Roese #define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918) 13529b103c7SStefan Roese #define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920) 13629b103c7SStefan Roese #define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058) 13729b103c7SStefan Roese #define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C) 13829b103c7SStefan Roese #define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810) 13929b103c7SStefan Roese #define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834) 14029b103c7SStefan Roese #define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838) 14129b103c7SStefan Roese #define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C) 14229b103c7SStefan Roese #define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840) 14329b103c7SStefan Roese 14429b103c7SStefan Roese #define MV_ETH_BASE_ADDR (0x72000) 14529b103c7SStefan Roese #define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \ 14629b103c7SStefan Roese 0x40000 + ((port) % 2) * 0x4000) 14729b103c7SStefan Roese #define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port) 14829b103c7SStefan Roese 14929b103c7SStefan Roese 15029b103c7SStefan Roese #define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04) 15129b103c7SStefan Roese #define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C) 15229b103c7SStefan Roese #define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18) 15329b103c7SStefan Roese #define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0) 15429b103c7SStefan Roese #define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4) 15529b103c7SStefan Roese #define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20) 15629b103c7SStefan Roese #define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38) 15729b103c7SStefan Roese #define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0) 15829b103c7SStefan Roese 15929b103c7SStefan Roese #define SERDES_LINE_MUX_REG_0_7 0x18270 16029b103c7SStefan Roese #define SERDES_LINE_MUX_REG_8_15 0x18274 16129b103c7SStefan Roese #define QSGMII_CONTROL_1_REG 0x18404 16229b103c7SStefan Roese 16329b103c7SStefan Roese /* SOC_CTRL_REG fields */ 16429b103c7SStefan Roese #define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) 16529b103c7SStefan Roese #define SCR_PEX_ENA_MASK(pex) (1 << pex) 16629b103c7SStefan Roese 16729b103c7SStefan Roese #define PCIE0_QUADX1_EN (1<<7) 16829b103c7SStefan Roese #define PCIE1_QUADX1_EN (1<<8) 16929b103c7SStefan Roese 17029b103c7SStefan Roese #define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) 17129b103c7SStefan Roese #define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) 17229b103c7SStefan Roese 17329b103c7SStefan Roese #define PCIE1_CLK_OUT_EN_OFF 5 17429b103c7SStefan Roese #define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF) 17529b103c7SStefan Roese 17629b103c7SStefan Roese #define PCIE0_CLK_OUT_EN_OFF 4 17729b103c7SStefan Roese #define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF) 17829b103c7SStefan Roese 17929b103c7SStefan Roese #define SCR_PEX0_4BY1_OFFS 7 18029b103c7SStefan Roese #define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS) 18129b103c7SStefan Roese 18229b103c7SStefan Roese #define SCR_PEX1_4BY1_OFFS 8 18329b103c7SStefan Roese #define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) 18429b103c7SStefan Roese 18529b103c7SStefan Roese 18629b103c7SStefan Roese #define MV_MISC_REGS_OFFSET (0x18200) 18729b103c7SStefan Roese #define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) 18829b103c7SStefan Roese #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) 18929b103c7SStefan Roese 19029b103c7SStefan Roese /* 19129b103c7SStefan Roese * PCI Express Control and Status Registers 19229b103c7SStefan Roese */ 19329b103c7SStefan Roese #define MAX_PEX_DEVICES 32 19429b103c7SStefan Roese #define MAX_PEX_FUNCS 8 19529b103c7SStefan Roese #define MAX_PEX_BUSSES 256 19629b103c7SStefan Roese 19729b103c7SStefan Roese #define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ 19829b103c7SStefan Roese #define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) 19929b103c7SStefan Roese 20029b103c7SStefan Roese #define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ 20129b103c7SStefan Roese #define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) 20229b103c7SStefan Roese 20329b103c7SStefan Roese #define PXSR_DL_DOWN 0x1 /* DL_Down indication. */ 20429b103c7SStefan Roese #define PXCAR_CONFIG_EN (1 << 31) 20529b103c7SStefan Roese #define PEX_STATUS_AND_COMMAND 0x004 20629b103c7SStefan Roese #define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */ 20729b103c7SStefan Roese 20829b103c7SStefan Roese /* PCI Express Configuration Address Register */ 20929b103c7SStefan Roese 21029b103c7SStefan Roese /* PEX_CFG_ADDR_REG (PXCAR) */ 21129b103c7SStefan Roese #define PXCAR_REG_NUM_OFFS 2 21229b103c7SStefan Roese #define PXCAR_REG_NUM_MAX 0x3F 21329b103c7SStefan Roese #define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) 21429b103c7SStefan Roese #define PXCAR_FUNC_NUM_OFFS 8 21529b103c7SStefan Roese #define PXCAR_FUNC_NUM_MAX 0x7 21629b103c7SStefan Roese #define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) 21729b103c7SStefan Roese #define PXCAR_DEVICE_NUM_OFFS 11 21829b103c7SStefan Roese #define PXCAR_DEVICE_NUM_MAX 0x1F 21929b103c7SStefan Roese #define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) 22029b103c7SStefan Roese #define PXCAR_BUS_NUM_OFFS 16 22129b103c7SStefan Roese #define PXCAR_BUS_NUM_MAX 0xFF 22229b103c7SStefan Roese #define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) 22329b103c7SStefan Roese #define PXCAR_EXT_REG_NUM_OFFS 24 22429b103c7SStefan Roese #define PXCAR_EXT_REG_NUM_MAX 0xF 22529b103c7SStefan Roese 22629b103c7SStefan Roese #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 22729b103c7SStefan Roese #define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) 22829b103c7SStefan Roese 22929b103c7SStefan Roese 23029b103c7SStefan Roese #define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60) 23129b103c7SStefan Roese #define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C) 23229b103c7SStefan Roese #define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70) 23329b103c7SStefan Roese #define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90) 23429b103c7SStefan Roese #define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00) 23529b103c7SStefan Roese #define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04) 23629b103c7SStefan Roese #define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10) 23729b103c7SStefan Roese #define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18) 23829b103c7SStefan Roese #define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20) 23929b103c7SStefan Roese #define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30) 24029b103c7SStefan Roese #define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C) 24129b103c7SStefan Roese #define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50) 24229b103c7SStefan Roese #define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60) 24329b103c7SStefan Roese #define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64) 24429b103c7SStefan Roese 24529b103c7SStefan Roese #define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */ 24629b103c7SStefan Roese #define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS) 24729b103c7SStefan Roese #define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS) 24829b103c7SStefan Roese #define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS) 24929b103c7SStefan Roese 25029b103c7SStefan Roese #define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8) 25129b103c7SStefan Roese #define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC) 25229b103c7SStefan Roese #define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900) 25329b103c7SStefan Roese 25429b103c7SStefan Roese #define PEX_CAPABILITY_REG 0x60 25529b103c7SStefan Roese #define PEX_DEV_CAPABILITY_REG 0x64 25629b103c7SStefan Roese #define PEX_DEV_CTRL_STAT_REG 0x68 25729b103c7SStefan Roese #define PEX_LINK_CAPABILITY_REG 0x6C 25829b103c7SStefan Roese #define PEX_LINK_CTRL_STAT_REG 0x70 25929b103c7SStefan Roese #define PEX_LINK_CTRL_STAT_2_REG 0x90 26029b103c7SStefan Roese 26129b103c7SStefan Roese #endif /* __BOARD_ENV_SPEC */ 262