183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
241d91011SPrabhakar Kushwaha /*
341d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc.
441d91011SPrabhakar Kushwaha */
541d91011SPrabhakar Kushwaha
641d91011SPrabhakar Kushwaha #include <common.h>
741d91011SPrabhakar Kushwaha #include <asm/processor.h>
841d91011SPrabhakar Kushwaha #include <asm/mmu.h>
941d91011SPrabhakar Kushwaha #include <asm/cache.h>
1041d91011SPrabhakar Kushwaha #include <asm/immap_85xx.h>
1141d91011SPrabhakar Kushwaha #include <asm/io.h>
1241d91011SPrabhakar Kushwaha #include <miiphy.h>
13b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
1441d91011SPrabhakar Kushwaha #include <fdt_support.h>
1541d91011SPrabhakar Kushwaha #include <fsl_mdio.h>
1641d91011SPrabhakar Kushwaha #include <tsec.h>
1741d91011SPrabhakar Kushwaha #include <mmc.h>
1841d91011SPrabhakar Kushwaha #include <netdev.h>
190b66513bSYork Sun #include <fsl_ifc.h>
2041d91011SPrabhakar Kushwaha #include <hwconfig.h>
2141d91011SPrabhakar Kushwaha #include <i2c.h>
225614e71bSYork Sun #include <fsl_ddr_sdram.h>
2342a9e2feSAshish Kumar #include <jffs2/load_kernel.h>
2442a9e2feSAshish Kumar #include <mtd_node.h>
2542a9e2feSAshish Kumar #include <flash.h>
2641d91011SPrabhakar Kushwaha
2741d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI
2841d91011SPrabhakar Kushwaha #include <pci.h>
2941d91011SPrabhakar Kushwaha #include <asm/fsl_pci.h>
3041d91011SPrabhakar Kushwaha #endif
3141d91011SPrabhakar Kushwaha
3241d91011SPrabhakar Kushwaha #include "../common/qixis.h"
3341d91011SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR;
3441d91011SPrabhakar Kushwaha
3541d91011SPrabhakar Kushwaha
board_early_init_f(void)3641d91011SPrabhakar Kushwaha int board_early_init_f(void)
3741d91011SPrabhakar Kushwaha {
3839b0bbbbSJaiprakash Singh struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
3941d91011SPrabhakar Kushwaha
4039b0bbbbSJaiprakash Singh setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
4141d91011SPrabhakar Kushwaha
4241d91011SPrabhakar Kushwaha return 0;
4341d91011SPrabhakar Kushwaha }
4441d91011SPrabhakar Kushwaha
board_config_serdes_mux(void)4541d91011SPrabhakar Kushwaha void board_config_serdes_mux(void)
4641d91011SPrabhakar Kushwaha {
4741d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
4841d91011SPrabhakar Kushwaha u32 pordevsr = in_be32(&gur->pordevsr);
4941d91011SPrabhakar Kushwaha u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
5041d91011SPrabhakar Kushwaha MPC85xx_PORDEVSR_IO_SEL_SHIFT;
5141d91011SPrabhakar Kushwaha
5241d91011SPrabhakar Kushwaha switch (srds_cfg) {
5341d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
5441d91011SPrabhakar Kushwaha case 1:
5541d91011SPrabhakar Kushwaha case 2:
5641d91011SPrabhakar Kushwaha case 3:
5741d91011SPrabhakar Kushwaha case 4:
5841d91011SPrabhakar Kushwaha case 5:
5941d91011SPrabhakar Kushwaha case 22:
6041d91011SPrabhakar Kushwaha case 23:
6141d91011SPrabhakar Kushwaha case 24:
6241d91011SPrabhakar Kushwaha case 25:
6341d91011SPrabhakar Kushwaha case 26:
6441d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x03);
6541d91011SPrabhakar Kushwaha break;
6641d91011SPrabhakar Kushwaha
6741d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 CPRI 1 */
6841d91011SPrabhakar Kushwaha case 6:
6941d91011SPrabhakar Kushwaha case 7:
7041d91011SPrabhakar Kushwaha case 8:
7141d91011SPrabhakar Kushwaha case 9:
7241d91011SPrabhakar Kushwaha case 10:
7341d91011SPrabhakar Kushwaha case 27:
7441d91011SPrabhakar Kushwaha case 28:
7541d91011SPrabhakar Kushwaha case 29:
7641d91011SPrabhakar Kushwaha case 30:
7741d91011SPrabhakar Kushwaha case 31:
7841d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x01);
7941d91011SPrabhakar Kushwaha break;
8041d91011SPrabhakar Kushwaha
8141d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 SGMII2 */
8241d91011SPrabhakar Kushwaha case 11:
8341d91011SPrabhakar Kushwaha case 32:
8441d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x00);
8541d91011SPrabhakar Kushwaha break;
8641d91011SPrabhakar Kushwaha
8741d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
8841d91011SPrabhakar Kushwaha case 12:
8941d91011SPrabhakar Kushwaha case 13:
9041d91011SPrabhakar Kushwaha case 14:
9141d91011SPrabhakar Kushwaha case 15:
9241d91011SPrabhakar Kushwaha case 16:
9341d91011SPrabhakar Kushwaha case 33:
9441d91011SPrabhakar Kushwaha case 34:
9541d91011SPrabhakar Kushwaha case 35:
9641d91011SPrabhakar Kushwaha case 36:
9741d91011SPrabhakar Kushwaha case 37:
9841d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x07);
9941d91011SPrabhakar Kushwaha break;
10041d91011SPrabhakar Kushwaha
10141d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 SGMII1 CPRI 1 */
10241d91011SPrabhakar Kushwaha case 17:
10341d91011SPrabhakar Kushwaha case 18:
10441d91011SPrabhakar Kushwaha case 19:
10541d91011SPrabhakar Kushwaha case 20:
10641d91011SPrabhakar Kushwaha case 21:
10741d91011SPrabhakar Kushwaha case 38:
10841d91011SPrabhakar Kushwaha case 39:
10941d91011SPrabhakar Kushwaha case 40:
11041d91011SPrabhakar Kushwaha case 41:
11141d91011SPrabhakar Kushwaha case 42:
11241d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x05);
11341d91011SPrabhakar Kushwaha break;
11441d91011SPrabhakar Kushwaha
11541d91011SPrabhakar Kushwaha /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
11641d91011SPrabhakar Kushwaha case 43:
11741d91011SPrabhakar Kushwaha case 44:
11841d91011SPrabhakar Kushwaha case 45:
11941d91011SPrabhakar Kushwaha case 46:
12041d91011SPrabhakar Kushwaha case 47:
12141d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
12241d91011SPrabhakar Kushwaha break;
12341d91011SPrabhakar Kushwaha
12441d91011SPrabhakar Kushwaha
12541d91011SPrabhakar Kushwaha default:
12641d91011SPrabhakar Kushwaha break;
12741d91011SPrabhakar Kushwaha }
12841d91011SPrabhakar Kushwaha }
12941d91011SPrabhakar Kushwaha
130f9d379a7SPriyanka Jain /* Configure DSP DDR controller */
dsp_ddr_configure(void)131f9d379a7SPriyanka Jain void dsp_ddr_configure(void)
132f9d379a7SPriyanka Jain {
133f9d379a7SPriyanka Jain /*
134f9d379a7SPriyanka Jain *There are separate DDR-controllers for DSP and PowerPC side DDR.
135f9d379a7SPriyanka Jain *copy the ddr controller settings from PowerPC side DDR controller
136f9d379a7SPriyanka Jain *to the DSP DDR controller as connected DDR memories are similar.
137f9d379a7SPriyanka Jain */
1389a17eb5bSYork Sun struct ccsr_ddr __iomem *pa_ddr =
1399a17eb5bSYork Sun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
1409a17eb5bSYork Sun struct ccsr_ddr temp_ddr;
1419a17eb5bSYork Sun struct ccsr_ddr __iomem *dsp_ddr =
1429a17eb5bSYork Sun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
143f9d379a7SPriyanka Jain
1449a17eb5bSYork Sun memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
145f9d379a7SPriyanka Jain temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
146f9d379a7SPriyanka Jain temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
1479a17eb5bSYork Sun memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
148f9d379a7SPriyanka Jain dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
149f9d379a7SPriyanka Jain }
150f9d379a7SPriyanka Jain
board_early_init_r(void)15141d91011SPrabhakar Kushwaha int board_early_init_r(void)
15241d91011SPrabhakar Kushwaha {
153e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH
15441d91011SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
1559d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1);
15641d91011SPrabhakar Kushwaha
15741d91011SPrabhakar Kushwaha /*
15841d91011SPrabhakar Kushwaha * Remap Boot flash region to caching-inhibited
15941d91011SPrabhakar Kushwaha * so that flash can be erased properly.
16041d91011SPrabhakar Kushwaha */
16141d91011SPrabhakar Kushwaha
16241d91011SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */
16341d91011SPrabhakar Kushwaha flush_dcache();
16441d91011SPrabhakar Kushwaha invalidate_icache();
16541d91011SPrabhakar Kushwaha
1669d045682SYork Sun if (flash_esel == -1) {
1679d045682SYork Sun /* very unlikely unless something is messed up */
1689d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n");
1699d045682SYork Sun flash_esel = 2; /* give our best effort to continue */
1709d045682SYork Sun } else {
17141d91011SPrabhakar Kushwaha /* invalidate existing TLB entry for flash */
17241d91011SPrabhakar Kushwaha disable_tlb(flash_esel);
1739d045682SYork Sun }
17441d91011SPrabhakar Kushwaha
17541d91011SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
17641d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
17741d91011SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_64M, 1);
17841d91011SPrabhakar Kushwaha
17941d91011SPrabhakar Kushwaha set_tlb(1, flashbase + 0x4000000,
18041d91011SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
18141d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
18241d91011SPrabhakar Kushwaha 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
18341d91011SPrabhakar Kushwaha #endif
18441d91011SPrabhakar Kushwaha board_config_serdes_mux();
185f9d379a7SPriyanka Jain dsp_ddr_configure();
18641d91011SPrabhakar Kushwaha return 0;
18741d91011SPrabhakar Kushwaha }
18841d91011SPrabhakar Kushwaha
18941d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI
pci_init_board(void)19041d91011SPrabhakar Kushwaha void pci_init_board(void)
19141d91011SPrabhakar Kushwaha {
19241d91011SPrabhakar Kushwaha fsl_pcie_init_board(0);
19341d91011SPrabhakar Kushwaha }
19441d91011SPrabhakar Kushwaha #endif /* ifdef CONFIG_PCI */
19541d91011SPrabhakar Kushwaha
checkboard(void)19641d91011SPrabhakar Kushwaha int checkboard(void)
19741d91011SPrabhakar Kushwaha {
19841d91011SPrabhakar Kushwaha struct cpu_type *cpu;
19941d91011SPrabhakar Kushwaha u8 sw;
20041d91011SPrabhakar Kushwaha
20167ac13b1SSimon Glass cpu = gd->arch.cpu;
20241d91011SPrabhakar Kushwaha printf("Board: %sQDS\n", cpu->name);
20341d91011SPrabhakar Kushwaha
20441d91011SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
20541d91011SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
20641d91011SPrabhakar Kushwaha
20741d91011SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]);
20841d91011SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
20941d91011SPrabhakar Kushwaha
21041d91011SPrabhakar Kushwaha printf("IFC chip select:");
21141d91011SPrabhakar Kushwaha switch (sw) {
21241d91011SPrabhakar Kushwaha case 0:
21341d91011SPrabhakar Kushwaha printf("NOR\n");
21441d91011SPrabhakar Kushwaha break;
21541d91011SPrabhakar Kushwaha case 2:
21641d91011SPrabhakar Kushwaha printf("Promjet\n");
21741d91011SPrabhakar Kushwaha break;
21841d91011SPrabhakar Kushwaha case 4:
21941d91011SPrabhakar Kushwaha printf("NAND\n");
22041d91011SPrabhakar Kushwaha break;
22141d91011SPrabhakar Kushwaha default:
22241d91011SPrabhakar Kushwaha printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
22341d91011SPrabhakar Kushwaha break;
22441d91011SPrabhakar Kushwaha }
22541d91011SPrabhakar Kushwaha
22641d91011SPrabhakar Kushwaha return 0;
22741d91011SPrabhakar Kushwaha }
22841d91011SPrabhakar Kushwaha
board_eth_init(bd_t * bis)22941d91011SPrabhakar Kushwaha int board_eth_init(bd_t *bis)
23041d91011SPrabhakar Kushwaha {
23189c97842SBin Meng #ifdef CONFIG_TSEC_ENET
23241d91011SPrabhakar Kushwaha struct fsl_pq_mdio_info mdio_info;
23341d91011SPrabhakar Kushwaha struct tsec_info_struct tsec_info[4];
23441d91011SPrabhakar Kushwaha int num = 0;
23541d91011SPrabhakar Kushwaha
23641d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC1
23741d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 1);
23841d91011SPrabhakar Kushwaha num++;
23941d91011SPrabhakar Kushwaha
24041d91011SPrabhakar Kushwaha #endif
24141d91011SPrabhakar Kushwaha
24241d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC2
24341d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 2);
24441d91011SPrabhakar Kushwaha num++;
24541d91011SPrabhakar Kushwaha #endif
24641d91011SPrabhakar Kushwaha
24741d91011SPrabhakar Kushwaha mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
24841d91011SPrabhakar Kushwaha mdio_info.name = DEFAULT_MII_NAME;
24941d91011SPrabhakar Kushwaha
25041d91011SPrabhakar Kushwaha fsl_pq_mdio_init(bis, &mdio_info);
25141d91011SPrabhakar Kushwaha tsec_eth_init(bis, tsec_info, num);
25289c97842SBin Meng #endif
25341d91011SPrabhakar Kushwaha
25441d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI
25541d91011SPrabhakar Kushwaha pci_eth_init(bis);
25641d91011SPrabhakar Kushwaha #endif
25741d91011SPrabhakar Kushwaha
25841d91011SPrabhakar Kushwaha return 0;
25941d91011SPrabhakar Kushwaha }
26041d91011SPrabhakar Kushwaha
26141d91011SPrabhakar Kushwaha #define USBMUX_SEL_MASK 0xc0
26241d91011SPrabhakar Kushwaha #define USBMUX_SEL_UART2 0xc0
26341d91011SPrabhakar Kushwaha #define USBMUX_SEL_USB 0x40
26441d91011SPrabhakar Kushwaha #define SPIMUX_SEL_UART3 0x80
26541d91011SPrabhakar Kushwaha #define GPS_MUX_SEL_GPS 0x40
26641d91011SPrabhakar Kushwaha
26741d91011SPrabhakar Kushwaha #define TSEC_1588_CLKIN_MASK 0x03
26841d91011SPrabhakar Kushwaha #define CON_XCVR_REF_CLK 0x00
26941d91011SPrabhakar Kushwaha
misc_init_r(void)27041d91011SPrabhakar Kushwaha int misc_init_r(void)
27141d91011SPrabhakar Kushwaha {
27241d91011SPrabhakar Kushwaha u8 val;
27341d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
27441d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr);
2758bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
27641d91011SPrabhakar Kushwaha
27741d91011SPrabhakar Kushwaha /*Configure 1588 clock-in source from RF Card*/
27841d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]);
27941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5],
28041d91011SPrabhakar Kushwaha (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
28141d91011SPrabhakar Kushwaha
28241d91011SPrabhakar Kushwaha if (hwconfig("uart2") && hwconfig("usb1")) {
28341d91011SPrabhakar Kushwaha printf("UART2 and USB cannot work together on the board\n");
28441d91011SPrabhakar Kushwaha printf("Remove one from hwconfig and reset\n");
28541d91011SPrabhakar Kushwaha } else {
28641d91011SPrabhakar Kushwaha if (hwconfig("uart2")) {
28741d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]);
28841d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5],
28941d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
29041d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3,
29141d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_USB_SEL_MASK);
29241d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
29341d91011SPrabhakar Kushwaha } else {
29441d91011SPrabhakar Kushwaha /* By default USB should be selected.
29541d91011SPrabhakar Kushwaha * Programming FPGA to select USB. */
29641d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]);
29741d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5],
29841d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
29941d91011SPrabhakar Kushwaha }
30041d91011SPrabhakar Kushwaha
30141d91011SPrabhakar Kushwaha }
30241d91011SPrabhakar Kushwaha
30341d91011SPrabhakar Kushwaha if (hwconfig("sim")) {
30441d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K ||
30541d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR ||
30641d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) {
30741d91011SPrabhakar Kushwaha
30841d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]);
30941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
31041d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr,
31141d91011SPrabhakar Kushwaha MPC85xx_PMUXCR0_SIM_SEL_MASK);
31241d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
31341d91011SPrabhakar Kushwaha }
31441d91011SPrabhakar Kushwaha }
31541d91011SPrabhakar Kushwaha
31641d91011SPrabhakar Kushwaha if (hwconfig("uart3")) {
31741d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K ||
31841d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR ||
31941d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC) {
32041d91011SPrabhakar Kushwaha
32141d91011SPrabhakar Kushwaha /* UART3 and SPI1 (Flashes) are muxed together */
32241d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]);
32341d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
32441d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3,
32541d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_UART3_SEL_MASK);
32641d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
32741d91011SPrabhakar Kushwaha
32841d91011SPrabhakar Kushwaha /* MUX to select UART3 connection to J24 header
32941d91011SPrabhakar Kushwaha * or to GPS */
33041d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[6]);
33141d91011SPrabhakar Kushwaha if (hwconfig("gps"))
33241d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6],
33341d91011SPrabhakar Kushwaha (val | GPS_MUX_SEL_GPS));
33441d91011SPrabhakar Kushwaha else
33541d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6],
33641d91011SPrabhakar Kushwaha (val & ~(GPS_MUX_SEL_GPS)));
33741d91011SPrabhakar Kushwaha }
33841d91011SPrabhakar Kushwaha }
33941d91011SPrabhakar Kushwaha return 0;
34041d91011SPrabhakar Kushwaha }
34141d91011SPrabhakar Kushwaha
fdt_del_node_compat(void * blob,const char * compatible)34241d91011SPrabhakar Kushwaha void fdt_del_node_compat(void *blob, const char *compatible)
34341d91011SPrabhakar Kushwaha {
34441d91011SPrabhakar Kushwaha int err;
34541d91011SPrabhakar Kushwaha int off = fdt_node_offset_by_compatible(blob, -1, compatible);
34641d91011SPrabhakar Kushwaha if (off < 0) {
34741d91011SPrabhakar Kushwaha printf("WARNING: could not find compatible node %s: %s.\n",
34841d91011SPrabhakar Kushwaha compatible, fdt_strerror(off));
34941d91011SPrabhakar Kushwaha return;
35041d91011SPrabhakar Kushwaha }
35141d91011SPrabhakar Kushwaha err = fdt_del_node(blob, off);
35241d91011SPrabhakar Kushwaha if (err < 0) {
35341d91011SPrabhakar Kushwaha printf("WARNING: could not remove %s: %s.\n",
35441d91011SPrabhakar Kushwaha compatible, fdt_strerror(err));
35541d91011SPrabhakar Kushwaha }
35641d91011SPrabhakar Kushwaha }
35741d91011SPrabhakar Kushwaha
35841d91011SPrabhakar Kushwaha #if defined(CONFIG_OF_BOARD_SETUP)
35942a9e2feSAshish Kumar #ifdef CONFIG_FDT_FIXUP_PARTITIONS
360*b35fb6acSMasahiro Yamada static const struct node_info nodes[] = {
36142a9e2feSAshish Kumar { "cfi-flash", MTD_DEV_TYPE_NOR, },
36242a9e2feSAshish Kumar { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
36342a9e2feSAshish Kumar };
36442a9e2feSAshish Kumar #endif
ft_board_setup(void * blob,bd_t * bd)365e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd)
36641d91011SPrabhakar Kushwaha {
36741d91011SPrabhakar Kushwaha phys_addr_t base;
36841d91011SPrabhakar Kushwaha phys_size_t size;
36941d91011SPrabhakar Kushwaha
37041d91011SPrabhakar Kushwaha ft_cpu_setup(blob, bd);
37141d91011SPrabhakar Kushwaha
372723806ccSSimon Glass base = env_get_bootm_low();
373723806ccSSimon Glass size = env_get_bootm_size();
37441d91011SPrabhakar Kushwaha
37541d91011SPrabhakar Kushwaha #if defined(CONFIG_PCI)
37641d91011SPrabhakar Kushwaha FT_FSL_PCI_SETUP;
37741d91011SPrabhakar Kushwaha #endif
37841d91011SPrabhakar Kushwaha
37941d91011SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size);
38042a9e2feSAshish Kumar #ifdef CONFIG_FDT_FIXUP_PARTITIONS
38142a9e2feSAshish Kumar fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
38242a9e2feSAshish Kumar #endif
38341d91011SPrabhakar Kushwaha
38441d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
38541d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr);
3868bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
38741d91011SPrabhakar Kushwaha
38841d91011SPrabhakar Kushwaha if (!(hwconfig("uart2") && hwconfig("usb1"))) {
38941d91011SPrabhakar Kushwaha /* If uart2 is there in hwconfig remove usb node from
39041d91011SPrabhakar Kushwaha * device tree */
39141d91011SPrabhakar Kushwaha
39241d91011SPrabhakar Kushwaha if (hwconfig("uart2")) {
39341d91011SPrabhakar Kushwaha /* remove dts usb node */
39441d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl-usb2-dr");
39541d91011SPrabhakar Kushwaha } else {
396a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd);
39741d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial2");
39841d91011SPrabhakar Kushwaha }
39941d91011SPrabhakar Kushwaha }
40041d91011SPrabhakar Kushwaha
40141d91011SPrabhakar Kushwaha if (hwconfig("uart3")) {
40241d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K ||
40341d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR ||
40441d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC)
40541d91011SPrabhakar Kushwaha /* Delete SPI node from the device tree */
40641d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "spi1");
40741d91011SPrabhakar Kushwaha } else
40841d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial3");
40941d91011SPrabhakar Kushwaha
41041d91011SPrabhakar Kushwaha if (hwconfig("sim")) {
41141d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K ||
41241d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR ||
41341d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) {
41441d91011SPrabhakar Kushwaha
41541d91011SPrabhakar Kushwaha /* remove dts sdhc node */
41641d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,esdhc");
41741d91011SPrabhakar Kushwaha } else if (romloc == PORBMSR_ROMLOC_SDHC) {
41841d91011SPrabhakar Kushwaha
41941d91011SPrabhakar Kushwaha /* remove dts sim node */
42041d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,sim-v1.0");
42141d91011SPrabhakar Kushwaha printf("SIM & SDHC can't work together on the board");
42241d91011SPrabhakar Kushwaha printf("\nRemove sim from hwconfig and reset\n");
42341d91011SPrabhakar Kushwaha }
42441d91011SPrabhakar Kushwaha }
425e895a4b0SSimon Glass
426e895a4b0SSimon Glass return 0;
42741d91011SPrabhakar Kushwaha }
42841d91011SPrabhakar Kushwaha #endif
429