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/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape.c5 * Layerscape PCIe driver
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
41 return in_le32(pcie->ctrl + offset); in ctrl_readl()
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, in ctrl_writel() argument
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H A Dpcie_intel_fpga.c3 * Intel FPGA PCIe host controller driver
37 #define RP_CFG_ADDR(pcie, reg) \ argument
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \ argument
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \ argument
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \ argument
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf) \ argument
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H A Dpci-aardvark.c34 /* PCIe core registers */
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
135 * struct pcie_advk - Advk PCIe controller state
138 * @first_busno: This driver supports multiple PCIe controllers.
139 * first_busno stores the bus number of the PCIe root-port
140 * number which may vary depending on the PCIe setup
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
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H A Dpci_mvebu.c3 * PCIe driver for Marvell MVEBU SoCs
27 /* PCIe unit register offsets */
84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
91 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
94 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
98 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) in mvebu_pcie_set_local_bus_nr() argument
102 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
105 writel(stat, pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
108 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) in mvebu_pcie_set_local_dev_nr() argument
112 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
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H A Dpci_tegra.c6 * Based on NVIDIA PCIe driver
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
164 * entries, one entry per PCIe port. These field definitions and desired
195 struct tegra_pcie *pcie; member
240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, in afi_writel() argument
243 writel(value, pcie->afi.start + offset); in afi_writel()
246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
248 return readl(pcie->afi.start + offset); in afi_readl()
251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, in pads_writel() argument
254 writel(value, pcie->pads.start + offset); in pads_writel()
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H A Dpcie_layerscape_fixup.c5 * Layerscape PCIe driver
25 static int ls_pcie_next_lut_index(struct ls_pcie *pcie) in ls_pcie_next_lut_index() argument
27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()
28 return pcie->next_lut_index++; in ls_pcie_next_lut_index()
33 /* returns the next available streamid for pcie, -errno if failed */
44 static void lut_writel(struct ls_pcie *pcie, unsigned int value, in lut_writel() argument
47 if (pcie->big_endian) in lut_writel()
48 out_be32(pcie->lut + offset, value); in lut_writel()
50 out_le32(pcie->lut + offset, value); in lut_writel()
56 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, in ls_pcie_lut_set_mapping() argument
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H A Dpcie_dw_mvebu.c97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
134 * @pcie: Pointer to the PCI controller state
138 * @pci_addr: the pcie bus address for the translation entry
141 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, in pcie_dw_prog_outbound_atu() argument
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
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H A DKconfig30 bool "Enable Aardvark PCIe driver"
35 Say Y here if you want to enable PCIe controller support on
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
47 bool "Enable Aspeed PCIe driver"
51 Say Y here if you want to enable PCIe controller support on
60 PCIe host controllers, such as the one emulated by QEMU.
63 bool "Enable Armada-8K PCIe driver (DesignWare core)"
67 Say Y here if you want to enable PCIe controller support on
68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
72 bool "Renesas RCar Gen2 PCIe driver"
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H A Dpcie_xilinx.c15 * struct xilinx_pcie - Xilinx PCIe controller state
27 * pcie_xilinx_link_up() - Check whether the PCIe link is up
28 * @pcie: Pointer to the PCI controller state
30 * Checks whether the PCIe link for the given device is up or down.
34 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) in pcie_xilinx_link_up() argument
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
44 * @bdf: Identifies the PCIe device to access
48 * Calculates the address that should be accessed to perform a PCIe
49 * configuration space access for a given device identified by the PCIe
50 * controller device @pcie and the bus, device & function numbers in @bdf. If
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DPCIeSlot.interface.yaml2 This defines a PCIe slot to be exposed for system management. It includes
10 The PCIe generation of the slot
15 The maximum number of PCIe lanes supported by the slot
26 Whether this PCIe slot supports hotplug
31 Possible PCIe generations
35 PCIe v1.0 slot
39 PCIe v2.0 slot
43 PCIe v3.0 slot
47 PCIe v4.0 slot
51 PCIe v5.0 slot
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/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
17 see 'PCIE-PCI bridge hot-plug' section),
25 PCIE-PCI bridge hot-plug
27 Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug.
36 that is planned to have PCIE-PCI bridge hot-plugged in.
62 At the moment this capability is used only in QEMU generic PCIe root port
63 (-device pcie-root-port). Capability construction function takes all reservation
73 -device pcie-root-port,bus=pcie.0,id=rp1,slot=1 \
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/openbmc/u-boot/doc/
H A DREADME.srio-pcie-boot-corenet2 SRIO and PCIE Boot on Corenet Platforms
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DPCIeFunction.v1_6_0.json90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
95 "PCIe": "A standard PCIe function." string
105 "Physical": "A physical PCIe function.",
106 "Virtual": "A virtual PCIe function."
139 …e `CXLLogicalDevice` that represents the CXL logical device to which this PCIe function is assigne…
144 … "description": "An array of links to the drives that this PCIe function produces.",
148 … links to resources of type `Drive` that represent the drives associated with this PCIe function.",
156 … "description": "An array of links to the Ethernet interfaces that this PCIe function produces.",
160 …ype `EthernetInterface` that represent the network interfaces associated with this PCIe function.",
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H A DPCIeDevice.v1_19_0.json37 "description": "The CXL-specific properties of a PCIe device.",
38 "longDescription": "This type shall contain CXL-specific properties of a PCIe device.",
446 "MultiFunction": "A multi-function PCIe device.",
447 "Retimer": "A PCIe retimer device.",
448 …"Simulated": "A PCIe device that is not currently physically present, but is being simulated by th…
449 "SingleFunction": "A single-function PCIe device."
489 … "description": "An array of links to the chassis in which the PCIe device is contained.",
501 … "description": "An array of links to the remote PCIe ports to which this device is connected.",
505 …n an array of links to resources of type `Port` that represent the remote PCIe ports to which this…
520 "description": "An array of links to PCIe functions exposed by this device.",
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DPCIeFunction.v1_6_0.json90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
95 "PCIe": "A standard PCIe function." string
105 "Physical": "A physical PCIe function.",
106 "Virtual": "A virtual PCIe function."
139 …e `CXLLogicalDevice` that represents the CXL logical device to which this PCIe function is assigne…
144 … "description": "An array of links to the drives that this PCIe function produces.",
148 … links to resources of type `Drive` that represent the drives associated with this PCIe function.",
156 … "description": "An array of links to the Ethernet interfaces that this PCIe function produces.",
160 …ype `EthernetInterface` that represent the network interfaces associated with this PCIe function.",
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H A DPCIeDevice.v1_19_0.json37 "description": "The CXL-specific properties of a PCIe device.",
38 "longDescription": "This type shall contain CXL-specific properties of a PCIe device.",
446 "MultiFunction": "A multi-function PCIe device.",
447 "Retimer": "A PCIe retimer device.",
448 …"Simulated": "A PCIe device that is not currently physically present, but is being simulated by th…
449 "SingleFunction": "A single-function PCIe device."
489 … "description": "An array of links to the chassis in which the PCIe device is contained.",
501 … "description": "An array of links to the remote PCIe ports to which this device is connected.",
505 …n an array of links to resources of type `Port` that represent the remote PCIe ports to which this…
520 "description": "An array of links to PCIe functions exposed by this device.",
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/openbmc/u-boot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt1 Armada-8K PCIe DT details:
4 Armada-8k uses synopsis designware PCIe controller.
7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
12 define the mapping of the PCIe interface to interrupt numbers.
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
19 - phys : phandle to phy node associated with pcie controller.
20 - phy-names : must be "pcie-phy"
25 cpm_pcie0: pcie@f2600000 {
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/openbmc/qemu/docs/config/
H A Dq35-virtio-serial.cfg79 [device "pcie.1"]
80 driver = "pcie-root-port"
81 bus = "pcie.0"
87 [device "pcie.2"]
88 driver = "pcie-root-port"
89 bus = "pcie.0"
94 [device "pcie.3"]
95 driver = "pcie-root-port"
96 bus = "pcie.0"
101 [device "pcie.4"]
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H A Dq35-virtio-graphical.cfg74 [device "pcie.1"]
75 driver = "pcie-root-port"
76 bus = "pcie.0"
82 [device "pcie.2"]
83 driver = "pcie-root-port"
84 bus = "pcie.0"
89 [device "pcie.3"]
90 driver = "pcie-root-port"
91 bus = "pcie.0"
96 [device "pcie.4"]
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H A Dmach-virt-serial.cfg129 [device "pcie.1"]
130 driver = "pcie-root-port"
131 bus = "pcie.0"
137 [device "pcie.2"]
138 driver = "pcie-root-port"
139 bus = "pcie.0"
144 [device "pcie.3"]
145 driver = "pcie-root-port"
146 bus = "pcie.0"
151 [device "pcie.4"]
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H A Dmach-virt-graphical.cfg123 [device "pcie.1"]
124 driver = "pcie-root-port"
125 bus = "pcie.0"
131 [device "pcie.2"]
132 driver = "pcie-root-port"
133 bus = "pcie.0"
138 [device "pcie.3"]
139 driver = "pcie-root-port"
140 bus = "pcie.0"
145 [device "pcie.4"]
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/openbmc/u-boot/doc/mvebu/
H A Darmada-8k-memory.txt25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
35 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space.
39 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space.
41 0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space.
43 0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space.
45 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space.
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/openbmc/docs/designs/
H A Dredfish-pcie.md1 # Redfish PCIe Resources
11 Redfish has resources that describe PCIe devices and functions available on a
17 The Redfish PCIe resources are here:
27 This feature is intended to meet the Redfish requirements for the PCIe resources
34 model used in OpenBMC. The producer will provide the required PCIe values read
36 the Redfish PCIe resources.
42 gathering and caching PCIe hardware data and maintaining the D-Bus interfaces
43 and properties. The actual hardware mechanism that is used to gather the PCIe
49 the required data and send it to the PCIe daemon through IPMI, etc.
51 When reading hardware directly, the PCIe daemon must be aware of power state
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/openbmc/qemu/tests/qtest/
H A Dreadconfig-test.c309 { "ich9-pcie-port-1", "ioh3420" }, in test_docs_q35_emulated()
310 { "ich9-pcie-port-2", "ioh3420" }, in test_docs_q35_emulated()
311 { "ich9-pcie-port-3", "ioh3420" }, in test_docs_q35_emulated()
312 { "ich9-pcie-port-4", "ioh3420" }, in test_docs_q35_emulated()
337 { "pcie.1", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
338 { "pcie.2", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
339 { "pcie.3", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
340 { "pcie.4", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
341 { "pcie.5", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
342 { "pcie.6", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra210-p2371-2180.dts24 pcie-controller@01003000 {
48 nvidia,lanes = "pcie-5", "pcie-6";
53 pcie-x1 {
54 nvidia,lanes = "pcie-0";
55 nvidia,function = "pcie-x1";
59 pcie-x4 {
60 nvidia,lanes = "pcie-1", "pcie-2",
61 "pcie-3", "pcie-4";
62 nvidia,function = "pcie-x4";

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