183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2da419027SMinghuan Lian /*
3e809e747SPriyanka Jain * Copyright 2017 NXP
4e4e8cb71SMinghuan Lian * Copyright 2014-2015 Freescale Semiconductor, Inc.
5da419027SMinghuan Lian * Layerscape PCIe driver
6da419027SMinghuan Lian */
7da419027SMinghuan Lian
8da419027SMinghuan Lian #include <common.h>
9da419027SMinghuan Lian #include <asm/arch/fsl_serdes.h>
10da419027SMinghuan Lian #include <pci.h>
11da419027SMinghuan Lian #include <asm/io.h>
12e4e8cb71SMinghuan Lian #include <errno.h>
13e4e8cb71SMinghuan Lian #include <malloc.h>
1480afc63fSMinghuan Lian #include <dm.h>
156e2941d7SSimon Glass #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
166e2941d7SSimon Glass defined(CONFIG_ARM)
176e2941d7SSimon Glass #include <asm/arch/clock.h>
186e2941d7SSimon Glass #endif
19a7294abaSHou Zhiqiang #include "pcie_layerscape.h"
20e4e8cb71SMinghuan Lian
2180afc63fSMinghuan Lian DECLARE_GLOBAL_DATA_PTR;
2280afc63fSMinghuan Lian
2380afc63fSMinghuan Lian LIST_HEAD(ls_pcie_list);
2480afc63fSMinghuan Lian
dbi_readl(struct ls_pcie * pcie,unsigned int offset)2580afc63fSMinghuan Lian static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
2680afc63fSMinghuan Lian {
2780afc63fSMinghuan Lian return in_le32(pcie->dbi + offset);
2880afc63fSMinghuan Lian }
2980afc63fSMinghuan Lian
dbi_writel(struct ls_pcie * pcie,unsigned int value,unsigned int offset)3080afc63fSMinghuan Lian static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
3180afc63fSMinghuan Lian unsigned int offset)
3280afc63fSMinghuan Lian {
3380afc63fSMinghuan Lian out_le32(pcie->dbi + offset, value);
3480afc63fSMinghuan Lian }
3580afc63fSMinghuan Lian
ctrl_readl(struct ls_pcie * pcie,unsigned int offset)3680afc63fSMinghuan Lian static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
3780afc63fSMinghuan Lian {
3880afc63fSMinghuan Lian if (pcie->big_endian)
3980afc63fSMinghuan Lian return in_be32(pcie->ctrl + offset);
4080afc63fSMinghuan Lian else
4180afc63fSMinghuan Lian return in_le32(pcie->ctrl + offset);
4280afc63fSMinghuan Lian }
4380afc63fSMinghuan Lian
ctrl_writel(struct ls_pcie * pcie,unsigned int value,unsigned int offset)4480afc63fSMinghuan Lian static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
4580afc63fSMinghuan Lian unsigned int offset)
4680afc63fSMinghuan Lian {
4780afc63fSMinghuan Lian if (pcie->big_endian)
4880afc63fSMinghuan Lian out_be32(pcie->ctrl + offset, value);
4980afc63fSMinghuan Lian else
5080afc63fSMinghuan Lian out_le32(pcie->ctrl + offset, value);
5180afc63fSMinghuan Lian }
5280afc63fSMinghuan Lian
ls_pcie_ltssm(struct ls_pcie * pcie)5380afc63fSMinghuan Lian static int ls_pcie_ltssm(struct ls_pcie *pcie)
5480afc63fSMinghuan Lian {
5580afc63fSMinghuan Lian u32 state;
5680afc63fSMinghuan Lian uint svr;
5780afc63fSMinghuan Lian
5880afc63fSMinghuan Lian svr = get_svr();
5980afc63fSMinghuan Lian if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
6080afc63fSMinghuan Lian state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
6180afc63fSMinghuan Lian state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
6280afc63fSMinghuan Lian } else {
6380afc63fSMinghuan Lian state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
6480afc63fSMinghuan Lian }
6580afc63fSMinghuan Lian
6680afc63fSMinghuan Lian return state;
6780afc63fSMinghuan Lian }
6880afc63fSMinghuan Lian
ls_pcie_link_up(struct ls_pcie * pcie)6980afc63fSMinghuan Lian static int ls_pcie_link_up(struct ls_pcie *pcie)
7080afc63fSMinghuan Lian {
7180afc63fSMinghuan Lian int ltssm;
7280afc63fSMinghuan Lian
7380afc63fSMinghuan Lian ltssm = ls_pcie_ltssm(pcie);
7480afc63fSMinghuan Lian if (ltssm < LTSSM_PCIE_L0)
7580afc63fSMinghuan Lian return 0;
7680afc63fSMinghuan Lian
7780afc63fSMinghuan Lian return 1;
7880afc63fSMinghuan Lian }
7980afc63fSMinghuan Lian
ls_pcie_cfg0_set_busdev(struct ls_pcie * pcie,u32 busdev)8080afc63fSMinghuan Lian static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
8180afc63fSMinghuan Lian {
8280afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
8380afc63fSMinghuan Lian PCIE_ATU_VIEWPORT);
8480afc63fSMinghuan Lian dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
8580afc63fSMinghuan Lian }
8680afc63fSMinghuan Lian
ls_pcie_cfg1_set_busdev(struct ls_pcie * pcie,u32 busdev)8780afc63fSMinghuan Lian static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
8880afc63fSMinghuan Lian {
8980afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
9080afc63fSMinghuan Lian PCIE_ATU_VIEWPORT);
9180afc63fSMinghuan Lian dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
9280afc63fSMinghuan Lian }
9380afc63fSMinghuan Lian
ls_pcie_atu_outbound_set(struct ls_pcie * pcie,int idx,int type,u64 phys,u64 bus_addr,pci_size_t size)9480afc63fSMinghuan Lian static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
9580afc63fSMinghuan Lian u64 phys, u64 bus_addr, pci_size_t size)
9680afc63fSMinghuan Lian {
9780afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
9880afc63fSMinghuan Lian dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
9980afc63fSMinghuan Lian dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
10080afc63fSMinghuan Lian dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
10180afc63fSMinghuan Lian dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
10280afc63fSMinghuan Lian dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
10380afc63fSMinghuan Lian dbi_writel(pcie, type, PCIE_ATU_CR1);
10480afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
10580afc63fSMinghuan Lian }
10680afc63fSMinghuan Lian
10780afc63fSMinghuan Lian /* Use bar match mode and MEM type as default */
ls_pcie_atu_inbound_set(struct ls_pcie * pcie,int idx,int bar,u64 phys)10880afc63fSMinghuan Lian static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
10980afc63fSMinghuan Lian int bar, u64 phys)
11080afc63fSMinghuan Lian {
11180afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
11280afc63fSMinghuan Lian dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
11380afc63fSMinghuan Lian dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
11480afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
11580afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
11680afc63fSMinghuan Lian PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
11780afc63fSMinghuan Lian }
11880afc63fSMinghuan Lian
ls_pcie_dump_atu(struct ls_pcie * pcie)11980afc63fSMinghuan Lian static void ls_pcie_dump_atu(struct ls_pcie *pcie)
12080afc63fSMinghuan Lian {
12180afc63fSMinghuan Lian int i;
12280afc63fSMinghuan Lian
12380afc63fSMinghuan Lian for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
12480afc63fSMinghuan Lian dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
12580afc63fSMinghuan Lian PCIE_ATU_VIEWPORT);
12680afc63fSMinghuan Lian debug("iATU%d:\n", i);
12780afc63fSMinghuan Lian debug("\tLOWER PHYS 0x%08x\n",
12880afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
12980afc63fSMinghuan Lian debug("\tUPPER PHYS 0x%08x\n",
13080afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
13180afc63fSMinghuan Lian debug("\tLOWER BUS 0x%08x\n",
13280afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
13380afc63fSMinghuan Lian debug("\tUPPER BUS 0x%08x\n",
13480afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
13580afc63fSMinghuan Lian debug("\tLIMIT 0x%08x\n",
13680afc63fSMinghuan Lian readl(pcie->dbi + PCIE_ATU_LIMIT));
13780afc63fSMinghuan Lian debug("\tCR1 0x%08x\n",
13880afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_CR1));
13980afc63fSMinghuan Lian debug("\tCR2 0x%08x\n",
14080afc63fSMinghuan Lian dbi_readl(pcie, PCIE_ATU_CR2));
14180afc63fSMinghuan Lian }
14280afc63fSMinghuan Lian }
14380afc63fSMinghuan Lian
ls_pcie_setup_atu(struct ls_pcie * pcie)14480afc63fSMinghuan Lian static void ls_pcie_setup_atu(struct ls_pcie *pcie)
14580afc63fSMinghuan Lian {
14680afc63fSMinghuan Lian struct pci_region *io, *mem, *pref;
14780afc63fSMinghuan Lian unsigned long long offset = 0;
14880afc63fSMinghuan Lian int idx = 0;
14980afc63fSMinghuan Lian uint svr;
15080afc63fSMinghuan Lian
15180afc63fSMinghuan Lian svr = get_svr();
15280afc63fSMinghuan Lian if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
15380afc63fSMinghuan Lian offset = LS1021_PCIE_SPACE_OFFSET +
15480afc63fSMinghuan Lian LS1021_PCIE_SPACE_SIZE * pcie->idx;
15580afc63fSMinghuan Lian }
15680afc63fSMinghuan Lian
15780afc63fSMinghuan Lian /* ATU 0 : OUTBOUND : CFG0 */
15880afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
15980afc63fSMinghuan Lian PCIE_ATU_TYPE_CFG0,
16080afc63fSMinghuan Lian pcie->cfg_res.start + offset,
16180afc63fSMinghuan Lian 0,
16280afc63fSMinghuan Lian fdt_resource_size(&pcie->cfg_res) / 2);
16380afc63fSMinghuan Lian /* ATU 1 : OUTBOUND : CFG1 */
16480afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
16580afc63fSMinghuan Lian PCIE_ATU_TYPE_CFG1,
16680afc63fSMinghuan Lian pcie->cfg_res.start + offset +
16780afc63fSMinghuan Lian fdt_resource_size(&pcie->cfg_res) / 2,
16880afc63fSMinghuan Lian 0,
16980afc63fSMinghuan Lian fdt_resource_size(&pcie->cfg_res) / 2);
17080afc63fSMinghuan Lian
17180afc63fSMinghuan Lian pci_get_regions(pcie->bus, &io, &mem, &pref);
17280afc63fSMinghuan Lian idx = PCIE_ATU_REGION_INDEX1 + 1;
17380afc63fSMinghuan Lian
1743d8553f0SHou Zhiqiang /* Fix the pcie memory map for LS2088A series SoCs */
1753d8553f0SHou Zhiqiang svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
1763d8553f0SHou Zhiqiang if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
177e809e747SPriyanka Jain svr == SVR_LS2048A || svr == SVR_LS2044A ||
178e809e747SPriyanka Jain svr == SVR_LS2081A || svr == SVR_LS2041A) {
1793d8553f0SHou Zhiqiang if (io)
1803d8553f0SHou Zhiqiang io->phys_start = (io->phys_start &
1813d8553f0SHou Zhiqiang (PCIE_PHYS_SIZE - 1)) +
1823d8553f0SHou Zhiqiang LS2088A_PCIE1_PHYS_ADDR +
1833d8553f0SHou Zhiqiang LS2088A_PCIE_PHYS_SIZE * pcie->idx;
1843d8553f0SHou Zhiqiang if (mem)
1853d8553f0SHou Zhiqiang mem->phys_start = (mem->phys_start &
1863d8553f0SHou Zhiqiang (PCIE_PHYS_SIZE - 1)) +
1873d8553f0SHou Zhiqiang LS2088A_PCIE1_PHYS_ADDR +
1883d8553f0SHou Zhiqiang LS2088A_PCIE_PHYS_SIZE * pcie->idx;
1893d8553f0SHou Zhiqiang if (pref)
1903d8553f0SHou Zhiqiang pref->phys_start = (pref->phys_start &
1913d8553f0SHou Zhiqiang (PCIE_PHYS_SIZE - 1)) +
1923d8553f0SHou Zhiqiang LS2088A_PCIE1_PHYS_ADDR +
1933d8553f0SHou Zhiqiang LS2088A_PCIE_PHYS_SIZE * pcie->idx;
1943d8553f0SHou Zhiqiang }
1953d8553f0SHou Zhiqiang
19680afc63fSMinghuan Lian if (io)
19780afc63fSMinghuan Lian /* ATU : OUTBOUND : IO */
19880afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, idx++,
19980afc63fSMinghuan Lian PCIE_ATU_TYPE_IO,
20080afc63fSMinghuan Lian io->phys_start + offset,
20180afc63fSMinghuan Lian io->bus_start,
20280afc63fSMinghuan Lian io->size);
20380afc63fSMinghuan Lian
20480afc63fSMinghuan Lian if (mem)
20580afc63fSMinghuan Lian /* ATU : OUTBOUND : MEM */
20680afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, idx++,
20780afc63fSMinghuan Lian PCIE_ATU_TYPE_MEM,
20880afc63fSMinghuan Lian mem->phys_start + offset,
20980afc63fSMinghuan Lian mem->bus_start,
21080afc63fSMinghuan Lian mem->size);
21180afc63fSMinghuan Lian
21280afc63fSMinghuan Lian if (pref)
21380afc63fSMinghuan Lian /* ATU : OUTBOUND : pref */
21480afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, idx++,
21580afc63fSMinghuan Lian PCIE_ATU_TYPE_MEM,
21680afc63fSMinghuan Lian pref->phys_start + offset,
21780afc63fSMinghuan Lian pref->bus_start,
21880afc63fSMinghuan Lian pref->size);
21980afc63fSMinghuan Lian
22080afc63fSMinghuan Lian ls_pcie_dump_atu(pcie);
22180afc63fSMinghuan Lian }
22280afc63fSMinghuan Lian
22380afc63fSMinghuan Lian /* Return 0 if the address is valid, -errno if not valid */
ls_pcie_addr_valid(struct ls_pcie * pcie,pci_dev_t bdf)22480afc63fSMinghuan Lian static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
22580afc63fSMinghuan Lian {
22680afc63fSMinghuan Lian struct udevice *bus = pcie->bus;
22780afc63fSMinghuan Lian
228*87e0d2b9SXiaowei Bao if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
229*87e0d2b9SXiaowei Bao return -ENODEV;
230*87e0d2b9SXiaowei Bao
23180afc63fSMinghuan Lian if (!pcie->enabled)
23280afc63fSMinghuan Lian return -ENXIO;
23380afc63fSMinghuan Lian
23480afc63fSMinghuan Lian if (PCI_BUS(bdf) < bus->seq)
23580afc63fSMinghuan Lian return -EINVAL;
23680afc63fSMinghuan Lian
23780afc63fSMinghuan Lian if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
23880afc63fSMinghuan Lian return -EINVAL;
23980afc63fSMinghuan Lian
24080afc63fSMinghuan Lian if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
24180afc63fSMinghuan Lian return -EINVAL;
24280afc63fSMinghuan Lian
24380afc63fSMinghuan Lian return 0;
24480afc63fSMinghuan Lian }
24580afc63fSMinghuan Lian
ls_pcie_conf_address(struct udevice * bus,pci_dev_t bdf,uint offset,void ** paddress)246e434a90eSTuomas Tynkkynen int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
247e434a90eSTuomas Tynkkynen uint offset, void **paddress)
24880afc63fSMinghuan Lian {
249e434a90eSTuomas Tynkkynen struct ls_pcie *pcie = dev_get_priv(bus);
25080afc63fSMinghuan Lian u32 busdev;
25180afc63fSMinghuan Lian
252e434a90eSTuomas Tynkkynen if (ls_pcie_addr_valid(pcie, bdf))
253e434a90eSTuomas Tynkkynen return -EINVAL;
254e434a90eSTuomas Tynkkynen
255e434a90eSTuomas Tynkkynen if (PCI_BUS(bdf) == bus->seq) {
256e434a90eSTuomas Tynkkynen *paddress = pcie->dbi + offset;
257e434a90eSTuomas Tynkkynen return 0;
258e434a90eSTuomas Tynkkynen }
25980afc63fSMinghuan Lian
2603977dcd5SMinghuan Lian busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
26180afc63fSMinghuan Lian PCIE_ATU_DEV(PCI_DEV(bdf)) |
26280afc63fSMinghuan Lian PCIE_ATU_FUNC(PCI_FUNC(bdf));
26380afc63fSMinghuan Lian
26480afc63fSMinghuan Lian if (PCI_BUS(bdf) == bus->seq + 1) {
26580afc63fSMinghuan Lian ls_pcie_cfg0_set_busdev(pcie, busdev);
266e434a90eSTuomas Tynkkynen *paddress = pcie->cfg0 + offset;
26780afc63fSMinghuan Lian } else {
26880afc63fSMinghuan Lian ls_pcie_cfg1_set_busdev(pcie, busdev);
269e434a90eSTuomas Tynkkynen *paddress = pcie->cfg1 + offset;
27080afc63fSMinghuan Lian }
271e434a90eSTuomas Tynkkynen return 0;
27280afc63fSMinghuan Lian }
27380afc63fSMinghuan Lian
ls_pcie_read_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)27480afc63fSMinghuan Lian static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
27580afc63fSMinghuan Lian uint offset, ulong *valuep,
27680afc63fSMinghuan Lian enum pci_size_t size)
27780afc63fSMinghuan Lian {
278e434a90eSTuomas Tynkkynen return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
279e434a90eSTuomas Tynkkynen bdf, offset, valuep, size);
28080afc63fSMinghuan Lian }
28180afc63fSMinghuan Lian
ls_pcie_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)28280afc63fSMinghuan Lian static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
28380afc63fSMinghuan Lian uint offset, ulong value,
28480afc63fSMinghuan Lian enum pci_size_t size)
28580afc63fSMinghuan Lian {
286e434a90eSTuomas Tynkkynen return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
287e434a90eSTuomas Tynkkynen bdf, offset, value, size);
28880afc63fSMinghuan Lian }
28980afc63fSMinghuan Lian
29080afc63fSMinghuan Lian /* Clear multi-function bit */
ls_pcie_clear_multifunction(struct ls_pcie * pcie)29180afc63fSMinghuan Lian static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
29280afc63fSMinghuan Lian {
29380afc63fSMinghuan Lian writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
29480afc63fSMinghuan Lian }
29580afc63fSMinghuan Lian
29680afc63fSMinghuan Lian /* Fix class value */
ls_pcie_fix_class(struct ls_pcie * pcie)29780afc63fSMinghuan Lian static void ls_pcie_fix_class(struct ls_pcie *pcie)
29880afc63fSMinghuan Lian {
29980afc63fSMinghuan Lian writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
30080afc63fSMinghuan Lian }
30180afc63fSMinghuan Lian
30280afc63fSMinghuan Lian /* Drop MSG TLP except for Vendor MSG */
ls_pcie_drop_msg_tlp(struct ls_pcie * pcie)30380afc63fSMinghuan Lian static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
30480afc63fSMinghuan Lian {
30580afc63fSMinghuan Lian u32 val;
30680afc63fSMinghuan Lian
30780afc63fSMinghuan Lian val = dbi_readl(pcie, PCIE_STRFMR1);
30880afc63fSMinghuan Lian val &= 0xDFFFFFFF;
30980afc63fSMinghuan Lian dbi_writel(pcie, val, PCIE_STRFMR1);
31080afc63fSMinghuan Lian }
31180afc63fSMinghuan Lian
31280afc63fSMinghuan Lian /* Disable all bars in RC mode */
ls_pcie_disable_bars(struct ls_pcie * pcie)31380afc63fSMinghuan Lian static void ls_pcie_disable_bars(struct ls_pcie *pcie)
31480afc63fSMinghuan Lian {
31580afc63fSMinghuan Lian u32 sriov;
31680afc63fSMinghuan Lian
31780afc63fSMinghuan Lian sriov = in_le32(pcie->dbi + PCIE_SRIOV);
31880afc63fSMinghuan Lian
31980afc63fSMinghuan Lian /*
32080afc63fSMinghuan Lian * TODO: For PCIe controller with SRIOV, the method to disable bars
32180afc63fSMinghuan Lian * is different and more complex, so will add later.
32280afc63fSMinghuan Lian */
32380afc63fSMinghuan Lian if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
32480afc63fSMinghuan Lian return;
32580afc63fSMinghuan Lian
32680afc63fSMinghuan Lian dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
32780afc63fSMinghuan Lian dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
32880afc63fSMinghuan Lian dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
32980afc63fSMinghuan Lian }
33080afc63fSMinghuan Lian
ls_pcie_setup_ctrl(struct ls_pcie * pcie)33180afc63fSMinghuan Lian static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
33280afc63fSMinghuan Lian {
33380afc63fSMinghuan Lian ls_pcie_setup_atu(pcie);
33480afc63fSMinghuan Lian
33580afc63fSMinghuan Lian dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
33680afc63fSMinghuan Lian ls_pcie_fix_class(pcie);
33780afc63fSMinghuan Lian ls_pcie_clear_multifunction(pcie);
33880afc63fSMinghuan Lian ls_pcie_drop_msg_tlp(pcie);
33980afc63fSMinghuan Lian dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
34080afc63fSMinghuan Lian
34180afc63fSMinghuan Lian ls_pcie_disable_bars(pcie);
34280afc63fSMinghuan Lian }
34380afc63fSMinghuan Lian
ls_pcie_ep_setup_atu(struct ls_pcie * pcie)34480afc63fSMinghuan Lian static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
34580afc63fSMinghuan Lian {
34680afc63fSMinghuan Lian u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
34780afc63fSMinghuan Lian
34880afc63fSMinghuan Lian /* ATU 0 : INBOUND : map BAR0 */
34980afc63fSMinghuan Lian ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
35080afc63fSMinghuan Lian /* ATU 1 : INBOUND : map BAR1 */
35180afc63fSMinghuan Lian phys += PCIE_BAR1_SIZE;
35280afc63fSMinghuan Lian ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
35380afc63fSMinghuan Lian /* ATU 2 : INBOUND : map BAR2 */
35480afc63fSMinghuan Lian phys += PCIE_BAR2_SIZE;
35580afc63fSMinghuan Lian ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
35680afc63fSMinghuan Lian /* ATU 3 : INBOUND : map BAR4 */
35780afc63fSMinghuan Lian phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
35880afc63fSMinghuan Lian ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
35980afc63fSMinghuan Lian
36080afc63fSMinghuan Lian /* ATU 0 : OUTBOUND : map MEM */
36180afc63fSMinghuan Lian ls_pcie_atu_outbound_set(pcie, 0,
36280afc63fSMinghuan Lian PCIE_ATU_TYPE_MEM,
36380afc63fSMinghuan Lian pcie->cfg_res.start,
36480afc63fSMinghuan Lian 0,
36580afc63fSMinghuan Lian CONFIG_SYS_PCI_MEMORY_SIZE);
36680afc63fSMinghuan Lian }
36780afc63fSMinghuan Lian
36880afc63fSMinghuan Lian /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
ls_pcie_ep_setup_bar(void * bar_base,int bar,u32 size)36980afc63fSMinghuan Lian static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
37080afc63fSMinghuan Lian {
37180afc63fSMinghuan Lian /* The least inbound window is 4KiB */
37280afc63fSMinghuan Lian if (size < 4 * 1024)
37380afc63fSMinghuan Lian return;
37480afc63fSMinghuan Lian
37580afc63fSMinghuan Lian switch (bar) {
37680afc63fSMinghuan Lian case 0:
37780afc63fSMinghuan Lian writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
37880afc63fSMinghuan Lian break;
37980afc63fSMinghuan Lian case 1:
38080afc63fSMinghuan Lian writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
38180afc63fSMinghuan Lian break;
38280afc63fSMinghuan Lian case 2:
38380afc63fSMinghuan Lian writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
38480afc63fSMinghuan Lian writel(0, bar_base + PCI_BASE_ADDRESS_3);
38580afc63fSMinghuan Lian break;
38680afc63fSMinghuan Lian case 4:
38780afc63fSMinghuan Lian writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
38880afc63fSMinghuan Lian writel(0, bar_base + PCI_BASE_ADDRESS_5);
38980afc63fSMinghuan Lian break;
39080afc63fSMinghuan Lian default:
39180afc63fSMinghuan Lian break;
39280afc63fSMinghuan Lian }
39380afc63fSMinghuan Lian }
39480afc63fSMinghuan Lian
ls_pcie_ep_setup_bars(void * bar_base)39580afc63fSMinghuan Lian static void ls_pcie_ep_setup_bars(void *bar_base)
39680afc63fSMinghuan Lian {
39780afc63fSMinghuan Lian /* BAR0 - 32bit - 4K configuration */
39880afc63fSMinghuan Lian ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
39980afc63fSMinghuan Lian /* BAR1 - 32bit - 8K MSIX*/
40080afc63fSMinghuan Lian ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
40180afc63fSMinghuan Lian /* BAR2 - 64bit - 4K MEM desciptor */
40280afc63fSMinghuan Lian ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
40380afc63fSMinghuan Lian /* BAR4 - 64bit - 1M MEM*/
40480afc63fSMinghuan Lian ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
40580afc63fSMinghuan Lian }
40680afc63fSMinghuan Lian
ls_pcie_ep_enable_cfg(struct ls_pcie * pcie)407d170aca1SHou Zhiqiang static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
408d170aca1SHou Zhiqiang {
409d170aca1SHou Zhiqiang ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
410d170aca1SHou Zhiqiang }
411d170aca1SHou Zhiqiang
ls_pcie_setup_ep(struct ls_pcie * pcie)41280afc63fSMinghuan Lian static void ls_pcie_setup_ep(struct ls_pcie *pcie)
41380afc63fSMinghuan Lian {
41480afc63fSMinghuan Lian u32 sriov;
41580afc63fSMinghuan Lian
41680afc63fSMinghuan Lian sriov = readl(pcie->dbi + PCIE_SRIOV);
41780afc63fSMinghuan Lian if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
41880afc63fSMinghuan Lian int pf, vf;
41980afc63fSMinghuan Lian
42080afc63fSMinghuan Lian for (pf = 0; pf < PCIE_PF_NUM; pf++) {
42180afc63fSMinghuan Lian for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
42280afc63fSMinghuan Lian ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
42380afc63fSMinghuan Lian PCIE_PF_VF_CTRL);
42480afc63fSMinghuan Lian
42580afc63fSMinghuan Lian ls_pcie_ep_setup_bars(pcie->dbi);
42680afc63fSMinghuan Lian ls_pcie_ep_setup_atu(pcie);
42780afc63fSMinghuan Lian }
42880afc63fSMinghuan Lian }
42980afc63fSMinghuan Lian /* Disable CFG2 */
43080afc63fSMinghuan Lian ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
43180afc63fSMinghuan Lian } else {
43280afc63fSMinghuan Lian ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
43380afc63fSMinghuan Lian ls_pcie_ep_setup_atu(pcie);
43480afc63fSMinghuan Lian }
435d170aca1SHou Zhiqiang
436d170aca1SHou Zhiqiang ls_pcie_ep_enable_cfg(pcie);
43780afc63fSMinghuan Lian }
43880afc63fSMinghuan Lian
ls_pcie_probe(struct udevice * dev)43980afc63fSMinghuan Lian static int ls_pcie_probe(struct udevice *dev)
44080afc63fSMinghuan Lian {
44180afc63fSMinghuan Lian struct ls_pcie *pcie = dev_get_priv(dev);
44280afc63fSMinghuan Lian const void *fdt = gd->fdt_blob;
443e160f7d4SSimon Glass int node = dev_of_offset(dev);
44480afc63fSMinghuan Lian u16 link_sta;
4453d8553f0SHou Zhiqiang uint svr;
44680afc63fSMinghuan Lian int ret;
44789d8e131SHou Zhiqiang fdt_size_t cfg_size;
44880afc63fSMinghuan Lian
44980afc63fSMinghuan Lian pcie->bus = dev;
45080afc63fSMinghuan Lian
45180afc63fSMinghuan Lian ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
45280afc63fSMinghuan Lian "dbi", &pcie->dbi_res);
45380afc63fSMinghuan Lian if (ret) {
45480afc63fSMinghuan Lian printf("ls-pcie: resource \"dbi\" not found\n");
45580afc63fSMinghuan Lian return ret;
45680afc63fSMinghuan Lian }
45780afc63fSMinghuan Lian
45880afc63fSMinghuan Lian pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
45980afc63fSMinghuan Lian
46080afc63fSMinghuan Lian list_add(&pcie->list, &ls_pcie_list);
46180afc63fSMinghuan Lian
46280afc63fSMinghuan Lian pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
46380afc63fSMinghuan Lian if (!pcie->enabled) {
46480afc63fSMinghuan Lian printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
46580afc63fSMinghuan Lian return 0;
46680afc63fSMinghuan Lian }
46780afc63fSMinghuan Lian
46880afc63fSMinghuan Lian pcie->dbi = map_physmem(pcie->dbi_res.start,
46980afc63fSMinghuan Lian fdt_resource_size(&pcie->dbi_res),
47080afc63fSMinghuan Lian MAP_NOCACHE);
47180afc63fSMinghuan Lian
47280afc63fSMinghuan Lian ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
47380afc63fSMinghuan Lian "lut", &pcie->lut_res);
47480afc63fSMinghuan Lian if (!ret)
47580afc63fSMinghuan Lian pcie->lut = map_physmem(pcie->lut_res.start,
47680afc63fSMinghuan Lian fdt_resource_size(&pcie->lut_res),
47780afc63fSMinghuan Lian MAP_NOCACHE);
47880afc63fSMinghuan Lian
47980afc63fSMinghuan Lian ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
48080afc63fSMinghuan Lian "ctrl", &pcie->ctrl_res);
48180afc63fSMinghuan Lian if (!ret)
48280afc63fSMinghuan Lian pcie->ctrl = map_physmem(pcie->ctrl_res.start,
48380afc63fSMinghuan Lian fdt_resource_size(&pcie->ctrl_res),
48480afc63fSMinghuan Lian MAP_NOCACHE);
48580afc63fSMinghuan Lian if (!pcie->ctrl)
48680afc63fSMinghuan Lian pcie->ctrl = pcie->lut;
48780afc63fSMinghuan Lian
48880afc63fSMinghuan Lian if (!pcie->ctrl) {
48980afc63fSMinghuan Lian printf("%s: NOT find CTRL\n", dev->name);
49080afc63fSMinghuan Lian return -1;
49180afc63fSMinghuan Lian }
49280afc63fSMinghuan Lian
49380afc63fSMinghuan Lian ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
49480afc63fSMinghuan Lian "config", &pcie->cfg_res);
49580afc63fSMinghuan Lian if (ret) {
49680afc63fSMinghuan Lian printf("%s: resource \"config\" not found\n", dev->name);
49780afc63fSMinghuan Lian return ret;
49880afc63fSMinghuan Lian }
49980afc63fSMinghuan Lian
5003d8553f0SHou Zhiqiang /*
5013d8553f0SHou Zhiqiang * Fix the pcie memory map address and PF control registers address
5023d8553f0SHou Zhiqiang * for LS2088A series SoCs
5033d8553f0SHou Zhiqiang */
5043d8553f0SHou Zhiqiang svr = get_svr();
5053d8553f0SHou Zhiqiang svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
5063d8553f0SHou Zhiqiang if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
507e809e747SPriyanka Jain svr == SVR_LS2048A || svr == SVR_LS2044A ||
508e809e747SPriyanka Jain svr == SVR_LS2081A || svr == SVR_LS2041A) {
50989d8e131SHou Zhiqiang cfg_size = fdt_resource_size(&pcie->cfg_res);
5103d8553f0SHou Zhiqiang pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
5113d8553f0SHou Zhiqiang LS2088A_PCIE_PHYS_SIZE * pcie->idx;
51289d8e131SHou Zhiqiang pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
5133d8553f0SHou Zhiqiang pcie->ctrl = pcie->lut + 0x40000;
5143d8553f0SHou Zhiqiang }
5153d8553f0SHou Zhiqiang
51680afc63fSMinghuan Lian pcie->cfg0 = map_physmem(pcie->cfg_res.start,
51780afc63fSMinghuan Lian fdt_resource_size(&pcie->cfg_res),
51880afc63fSMinghuan Lian MAP_NOCACHE);
51980afc63fSMinghuan Lian pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
52080afc63fSMinghuan Lian
52180afc63fSMinghuan Lian pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
52280afc63fSMinghuan Lian
52380afc63fSMinghuan Lian debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
52480afc63fSMinghuan Lian dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
52580afc63fSMinghuan Lian (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
52680afc63fSMinghuan Lian pcie->big_endian);
52780afc63fSMinghuan Lian
5285bd3c9d5SXiaowei Bao pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
52980afc63fSMinghuan Lian
5305bd3c9d5SXiaowei Bao if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
5315bd3c9d5SXiaowei Bao printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
53280afc63fSMinghuan Lian ls_pcie_setup_ep(pcie);
5335bd3c9d5SXiaowei Bao } else {
5345bd3c9d5SXiaowei Bao printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
53580afc63fSMinghuan Lian ls_pcie_setup_ctrl(pcie);
5365bd3c9d5SXiaowei Bao }
53780afc63fSMinghuan Lian
53880afc63fSMinghuan Lian if (!ls_pcie_link_up(pcie)) {
53980afc63fSMinghuan Lian /* Let the user know there's no PCIe link */
54080afc63fSMinghuan Lian printf(": no link\n");
54180afc63fSMinghuan Lian return 0;
54280afc63fSMinghuan Lian }
54380afc63fSMinghuan Lian
54480afc63fSMinghuan Lian /* Print the negotiated PCIe link width */
54580afc63fSMinghuan Lian link_sta = readw(pcie->dbi + PCIE_LINK_STA);
54680afc63fSMinghuan Lian printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
54780afc63fSMinghuan Lian link_sta & PCIE_LINK_SPEED_MASK);
54880afc63fSMinghuan Lian
54980afc63fSMinghuan Lian return 0;
55080afc63fSMinghuan Lian }
55180afc63fSMinghuan Lian
55280afc63fSMinghuan Lian static const struct dm_pci_ops ls_pcie_ops = {
55380afc63fSMinghuan Lian .read_config = ls_pcie_read_config,
55480afc63fSMinghuan Lian .write_config = ls_pcie_write_config,
55580afc63fSMinghuan Lian };
55680afc63fSMinghuan Lian
55780afc63fSMinghuan Lian static const struct udevice_id ls_pcie_ids[] = {
55880afc63fSMinghuan Lian { .compatible = "fsl,ls-pcie" },
55980afc63fSMinghuan Lian { }
56080afc63fSMinghuan Lian };
56180afc63fSMinghuan Lian
56280afc63fSMinghuan Lian U_BOOT_DRIVER(pci_layerscape) = {
56380afc63fSMinghuan Lian .name = "pci_layerscape",
56480afc63fSMinghuan Lian .id = UCLASS_PCI,
56580afc63fSMinghuan Lian .of_match = ls_pcie_ids,
56680afc63fSMinghuan Lian .ops = &ls_pcie_ops,
56780afc63fSMinghuan Lian .probe = ls_pcie_probe,
56880afc63fSMinghuan Lian .priv_auto_alloc_size = sizeof(struct ls_pcie),
56980afc63fSMinghuan Lian };
570