125734281SStephen Warren/dts-v1/;
225734281SStephen Warren
325734281SStephen Warren#include "tegra210.dtsi"
425734281SStephen Warren
525734281SStephen Warren/ {
625734281SStephen Warren	model = "NVIDIA P2371-2180";
725734281SStephen Warren	compatible = "nvidia,p2371-2180", "nvidia,tegra210";
825734281SStephen Warren
925734281SStephen Warren	chosen {
1025734281SStephen Warren		stdout-path = &uarta;
1125734281SStephen Warren	};
1225734281SStephen Warren
1325734281SStephen Warren	aliases {
14eb631d7fSStephen Warren		i2c0 = "/i2c@7000d000";
15eb631d7fSStephen Warren		mmc0 = "/sdhci@700b0600";
16eb631d7fSStephen Warren		mmc1 = "/sdhci@700b0000";
17eb631d7fSStephen Warren		usb0 = "/usb@7d000000";
1825734281SStephen Warren	};
1925734281SStephen Warren
2025734281SStephen Warren	memory {
2125734281SStephen Warren		reg = <0x0 0x80000000 0x0 0xc0000000>;
2225734281SStephen Warren	};
2325734281SStephen Warren
24eb631d7fSStephen Warren	pcie-controller@01003000 {
25019bc625SStephen Warren		status = "okay";
26019bc625SStephen Warren
27019bc625SStephen Warren		pci@1,0 {
28019bc625SStephen Warren			status = "okay";
29019bc625SStephen Warren		};
30019bc625SStephen Warren
31019bc625SStephen Warren		pci@2,0 {
32019bc625SStephen Warren			status = "okay";
33019bc625SStephen Warren		};
34019bc625SStephen Warren	};
35019bc625SStephen Warren
36eb631d7fSStephen Warren	padctl@7009f000 {
37019bc625SStephen Warren		pinctrl-0 = <&padctl_default>;
38019bc625SStephen Warren		pinctrl-names = "default";
39019bc625SStephen Warren
40019bc625SStephen Warren		padctl_default: pinmux {
41019bc625SStephen Warren			xusb {
42019bc625SStephen Warren				nvidia,lanes = "otg-1", "otg-2";
43019bc625SStephen Warren				nvidia,function = "xusb";
44019bc625SStephen Warren				nvidia,iddq = <0>;
45019bc625SStephen Warren			};
46019bc625SStephen Warren
47019bc625SStephen Warren			usb3 {
48019bc625SStephen Warren				nvidia,lanes = "pcie-5", "pcie-6";
49019bc625SStephen Warren				nvidia,function = "usb3";
50019bc625SStephen Warren				nvidia,iddq = <0>;
51019bc625SStephen Warren			};
52019bc625SStephen Warren
53019bc625SStephen Warren			pcie-x1 {
54019bc625SStephen Warren				nvidia,lanes = "pcie-0";
55019bc625SStephen Warren				nvidia,function = "pcie-x1";
56019bc625SStephen Warren				nvidia,iddq = <0>;
57019bc625SStephen Warren			};
58019bc625SStephen Warren
59019bc625SStephen Warren			pcie-x4 {
60019bc625SStephen Warren				nvidia,lanes = "pcie-1", "pcie-2",
61019bc625SStephen Warren					       "pcie-3", "pcie-4";
62019bc625SStephen Warren				nvidia,function = "pcie-x4";
63019bc625SStephen Warren				nvidia,iddq = <0>;
64019bc625SStephen Warren			};
65019bc625SStephen Warren
66019bc625SStephen Warren			sata {
67019bc625SStephen Warren				nvidia,lanes = "sata-0";
68019bc625SStephen Warren				nvidia,function = "sata";
69019bc625SStephen Warren				nvidia,iddq = <0>;
70019bc625SStephen Warren			};
71019bc625SStephen Warren		};
72019bc625SStephen Warren	};
73019bc625SStephen Warren
74eb631d7fSStephen Warren	sdhci@700b0000 {
7525734281SStephen Warren		status = "okay";
7625734281SStephen Warren		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
7725734281SStephen Warren		power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
7825734281SStephen Warren		wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
7925734281SStephen Warren		bus-width = <4>;
8025734281SStephen Warren	};
8125734281SStephen Warren
82eb631d7fSStephen Warren	sdhci@700b0600 {
8325734281SStephen Warren		status = "okay";
8425734281SStephen Warren		bus-width = <8>;
859a06a1a3STom Warren		non-removable;
8625734281SStephen Warren	};
8725734281SStephen Warren
88eb631d7fSStephen Warren	i2c@7000d000 {
8925734281SStephen Warren		status = "okay";
9025734281SStephen Warren		clock-frequency = <400000>;
9125734281SStephen Warren	};
9225734281SStephen Warren
93eb631d7fSStephen Warren	usb@7d000000 {
9425734281SStephen Warren		status = "okay";
9525734281SStephen Warren		dr_mode = "otg";
9625734281SStephen Warren		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
9725734281SStephen Warren	};
9825734281SStephen Warren
9925734281SStephen Warren	clocks {
10025734281SStephen Warren		compatible = "simple-bus";
10125734281SStephen Warren		#address-cells = <1>;
10225734281SStephen Warren		#size-cells = <0>;
10325734281SStephen Warren
10425734281SStephen Warren		clk32k_in: clock@0 {
10525734281SStephen Warren			compatible = "fixed-clock";
10625734281SStephen Warren			reg = <0>;
10725734281SStephen Warren			#clock-cells = <0>;
10825734281SStephen Warren			clock-frequency = <32768>;
10925734281SStephen Warren		};
11025734281SStephen Warren	};
11125734281SStephen Warren};
112*f53dcc0eSSimon Glass
113*f53dcc0eSSimon Glass&uarta {
114*f53dcc0eSSimon Glass	status = "okay";
115*f53dcc0eSSimon Glass};
116