1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Marvell International Ltd.
4 *
5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
6 *
7 * Based on:
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <pci.h>
16 #include <asm/io.h>
17 #include <asm-generic/gpio.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* PCI Config space registers */
22 #define PCIE_CONFIG_BAR0 0x10
23 #define PCIE_LINK_STATUS_REG 0x80
24 #define PCIE_LINK_STATUS_SPEED_OFF 16
25 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
26 #define PCIE_LINK_STATUS_WIDTH_OFF 20
27 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
28
29 /* Resizable bar capability registers */
30 #define RESIZABLE_BAR_CAP 0x250
31 #define RESIZABLE_BAR_CTL0 0x254
32 #define RESIZABLE_BAR_CTL1 0x258
33
34 /* iATU registers */
35 #define PCIE_ATU_VIEWPORT 0x900
36 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
37 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
38 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
39 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
40 #define PCIE_ATU_CR1 0x904
41 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
42 #define PCIE_ATU_TYPE_IO (0x2 << 0)
43 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
44 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
45 #define PCIE_ATU_CR2 0x908
46 #define PCIE_ATU_ENABLE (0x1 << 31)
47 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
48 #define PCIE_ATU_LOWER_BASE 0x90C
49 #define PCIE_ATU_UPPER_BASE 0x910
50 #define PCIE_ATU_LIMIT 0x914
51 #define PCIE_ATU_LOWER_TARGET 0x918
52 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
53 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
54 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
55 #define PCIE_ATU_UPPER_TARGET 0x91C
56
57 #define PCIE_LINK_CAPABILITY 0x7C
58 #define PCIE_LINK_CTL_2 0xA0
59 #define TARGET_LINK_SPEED_MASK 0xF
60 #define LINK_SPEED_GEN_1 0x1
61 #define LINK_SPEED_GEN_2 0x2
62 #define LINK_SPEED_GEN_3 0x3
63
64 #define PCIE_GEN3_RELATED 0x890
65 #define GEN3_EQU_DISABLE (1 << 16)
66 #define GEN3_ZRXDC_NON_COMP (1 << 0)
67
68 #define PCIE_GEN3_EQU_CTRL 0x8A8
69 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
70
71 #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
72
73 #define PCIE_LINK_UP_TIMEOUT_MS 100
74
75 #define PCIE_GLOBAL_CONTROL 0x8000
76 #define PCIE_APP_LTSSM_EN (1 << 2)
77 #define PCIE_DEVICE_TYPE_OFFSET (4)
78 #define PCIE_DEVICE_TYPE_MASK (0xF)
79 #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
80 #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
81 #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
82
83 #define PCIE_GLOBAL_STATUS 0x8008
84 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
85 #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
86
87 #define PCIE_ARCACHE_TRC 0x8050
88 #define PCIE_AWCACHE_TRC 0x8054
89 #define ARCACHE_SHAREABLE_CACHEABLE 0x3511
90 #define AWCACHE_SHAREABLE_CACHEABLE 0x5311
91
92 #define LINK_SPEED_GEN_1 0x1
93 #define LINK_SPEED_GEN_2 0x2
94 #define LINK_SPEED_GEN_3 0x3
95
96 /**
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
98 *
99 * @ctrl_base: The base address of the register space
100 * @cfg_base: The base address of the configuration space
101 * @cfg_size: The size of the configuration space which is needed
102 * as it gets written into the PCIE_ATU_LIMIT register
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
106 * (PEX switches etc).
107 */
108 struct pcie_dw_mvebu {
109 void *ctrl_base;
110 void *cfg_base;
111 fdt_size_t cfg_size;
112 int first_busno;
113
114 /* IO and MEM PCI regions */
115 struct pci_region io;
116 struct pci_region mem;
117 };
118
pcie_dw_get_link_speed(const void * regs_base)119 static int pcie_dw_get_link_speed(const void *regs_base)
120 {
121 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
122 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
123 }
124
pcie_dw_get_link_width(const void * regs_base)125 static int pcie_dw_get_link_width(const void *regs_base)
126 {
127 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
128 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
129 }
130
131 /**
132 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
133 *
134 * @pcie: Pointer to the PCI controller state
135 * @index: ATU region index
136 * @type: ATU accsess type
137 * @cpu_addr: the physical address for the translation entry
138 * @pci_addr: the pcie bus address for the translation entry
139 * @size: the size of the translation entry
140 */
pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu * pcie,int index,int type,u64 cpu_addr,u64 pci_addr,u32 size)141 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
142 int type, u64 cpu_addr, u64 pci_addr,
143 u32 size)
144 {
145 writel(PCIE_ATU_REGION_OUTBOUND | index,
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT);
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
149 writel(lower_32_bits(cpu_addr + size - 1),
150 pcie->ctrl_base + PCIE_ATU_LIMIT);
151 writel(lower_32_bits(pci_addr),
152 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
153 writel(upper_32_bits(pci_addr),
154 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
155 writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
156 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
157 }
158
159 /**
160 * set_cfg_address() - Configure the PCIe controller config space access
161 *
162 * @pcie: Pointer to the PCI controller state
163 * @d: PCI device to access
164 * @where: Offset in the configuration space
165 *
166 * Configures the PCIe controller to access the configuration space of
167 * a specific PCIe device and returns the address to use for this
168 * access.
169 *
170 * Return: Address that can be used to access the configation space
171 * of the requested device / offset
172 */
set_cfg_address(struct pcie_dw_mvebu * pcie,pci_dev_t d,uint where)173 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
174 pci_dev_t d, uint where)
175 {
176 uintptr_t va_address;
177 u32 atu_type;
178
179 /*
180 * Region #0 is used for Outbound CFG space access.
181 * Direction = Outbound
182 * Region Index = 0
183 */
184
185 if (PCI_BUS(d) == (pcie->first_busno + 1))
186 /* For local bus, change TLP Type field to 4. */
187 atu_type = PCIE_ATU_TYPE_CFG0;
188 else
189 /* Otherwise, change TLP Type field to 5. */
190 atu_type = PCIE_ATU_TYPE_CFG1;
191
192 if (PCI_BUS(d) == pcie->first_busno) {
193 /* Accessing root port configuration space. */
194 va_address = (uintptr_t)pcie->ctrl_base;
195 } else {
196 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
197 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
198 atu_type, (u64)pcie->cfg_base,
199 d << 8, pcie->cfg_size);
200 va_address = (uintptr_t)pcie->cfg_base;
201 }
202
203 va_address += where & ~0x3;
204
205 return va_address;
206 }
207
208 /**
209 * pcie_dw_addr_valid() - Check for valid bus address
210 *
211 * @d: The PCI device to access
212 * @first_busno: Bus number of the PCIe controller root complex
213 *
214 * Return 1 (true) if the PCI device can be accessed by this controller.
215 *
216 * Return: 1 on valid, 0 on invalid
217 */
pcie_dw_addr_valid(pci_dev_t d,int first_busno)218 static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
219 {
220 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
221 return 0;
222 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
223 return 0;
224
225 return 1;
226 }
227
228 /**
229 * pcie_dw_mvebu_read_config() - Read from configuration space
230 *
231 * @bus: Pointer to the PCI bus
232 * @bdf: Identifies the PCIe device to access
233 * @offset: The offset into the device's configuration space
234 * @valuep: A pointer at which to store the read value
235 * @size: Indicates the size of access to perform
236 *
237 * Read a value of size @size from offset @offset within the configuration
238 * space of the device identified by the bus, device & function numbers in @bdf
239 * on the PCI bus @bus.
240 *
241 * Return: 0 on success
242 */
pcie_dw_mvebu_read_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)243 static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
244 uint offset, ulong *valuep,
245 enum pci_size_t size)
246 {
247 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
248 uintptr_t va_address;
249 ulong value;
250
251 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
252 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
253
254 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
255 debug("- out of range\n");
256 *valuep = pci_get_ff(size);
257 return 0;
258 }
259
260 va_address = set_cfg_address(pcie, bdf, offset);
261
262 value = readl(va_address);
263
264 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
265 *valuep = pci_conv_32_to_size(value, offset, size);
266
267 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
268 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
269 pcie->io.bus_start, pcie->io.size);
270
271 return 0;
272 }
273
274 /**
275 * pcie_dw_mvebu_write_config() - Write to configuration space
276 *
277 * @bus: Pointer to the PCI bus
278 * @bdf: Identifies the PCIe device to access
279 * @offset: The offset into the device's configuration space
280 * @value: The value to write
281 * @size: Indicates the size of access to perform
282 *
283 * Write the value @value of size @size from offset @offset within the
284 * configuration space of the device identified by the bus, device & function
285 * numbers in @bdf on the PCI bus @bus.
286 *
287 * Return: 0 on success
288 */
pcie_dw_mvebu_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)289 static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
290 uint offset, ulong value,
291 enum pci_size_t size)
292 {
293 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
294 uintptr_t va_address;
295 ulong old;
296
297 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
298 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
299 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
300
301 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
302 debug("- out of range\n");
303 return 0;
304 }
305
306 va_address = set_cfg_address(pcie, bdf, offset);
307
308 old = readl(va_address);
309 value = pci_conv_size_to_32(old, value, offset, size);
310 writel(value, va_address);
311
312 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
313 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
314 pcie->io.bus_start, pcie->io.size);
315
316 return 0;
317 }
318
319 /**
320 * pcie_dw_configure() - Configure link capabilities and speed
321 *
322 * @regs_base: A pointer to the PCIe controller registers
323 * @cap_speed: The capabilities and speed to configure
324 *
325 * Configure the link capabilities and speed in the PCIe root complex.
326 */
pcie_dw_configure(const void * regs_base,u32 cap_speed)327 static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
328 {
329 /*
330 * TODO (shadi@marvell.com, sr@denx.de):
331 * Need to read the serdes speed from the dts and according to it
332 * configure the PCIe gen
333 */
334
335 /* Set link to GEN 3 */
336 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
337 TARGET_LINK_SPEED_MASK, cap_speed);
338 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
339 TARGET_LINK_SPEED_MASK, cap_speed);
340 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
341 }
342
343 /**
344 * is_link_up() - Return the link state
345 *
346 * @regs_base: A pointer to the PCIe controller registers
347 *
348 * Return: 1 (true) for active line and 0 (false) for no link
349 */
is_link_up(const void * regs_base)350 static int is_link_up(const void *regs_base)
351 {
352 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
353 u32 reg;
354
355 reg = readl(regs_base + PCIE_GLOBAL_STATUS);
356 if ((reg & mask) == mask)
357 return 1;
358
359 return 0;
360 }
361
362 /**
363 * wait_link_up() - Wait for the link to come up
364 *
365 * @regs_base: A pointer to the PCIe controller registers
366 *
367 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
368 */
wait_link_up(const void * regs_base)369 static int wait_link_up(const void *regs_base)
370 {
371 unsigned long timeout;
372
373 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
374 while (!is_link_up(regs_base)) {
375 if (get_timer(0) > timeout)
376 return 0;
377 };
378
379 return 1;
380 }
381
382 /**
383 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
384 *
385 * @regs_base: A pointer to the PCIe controller registers
386 * @cap_speed: The capabilities and speed to configure
387 *
388 * Configure the PCIe controller root complex depending on the
389 * requested link capabilities and speed.
390 *
391 * Return: 1 (true) for active line and 0 (false) for no link
392 */
pcie_dw_mvebu_pcie_link_up(const void * regs_base,u32 cap_speed)393 static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
394 {
395 if (!is_link_up(regs_base)) {
396 /* Disable LTSSM state machine to enable configuration */
397 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
398 PCIE_APP_LTSSM_EN);
399 }
400
401 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
402 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
403 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
404
405 /* Set the PCIe master AXI attributes */
406 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
407 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
408
409 /* DW pre link configurations */
410 pcie_dw_configure(regs_base, cap_speed);
411
412 if (!is_link_up(regs_base)) {
413 /* Configuration done. Start LTSSM */
414 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
415 PCIE_APP_LTSSM_EN);
416 }
417
418 /* Check that link was established */
419 if (!wait_link_up(regs_base))
420 return 0;
421
422 /*
423 * Link can be established in Gen 1. still need to wait
424 * till MAC nagaotiation is completed
425 */
426 udelay(100);
427
428 return 1;
429 }
430
431 /**
432 * pcie_dw_set_host_bars() - Configure the host BARs
433 *
434 * @regs_base: A pointer to the PCIe controller registers
435 *
436 * Configure the host BARs of the PCIe controller root port so that
437 * PCI(e) devices may access the system memory.
438 */
pcie_dw_set_host_bars(const void * regs_base)439 static void pcie_dw_set_host_bars(const void *regs_base)
440 {
441 u32 size = gd->ram_size;
442 u64 max_size;
443 u32 reg;
444 u32 bar0;
445
446 /* Verify the maximal BAR size */
447 reg = readl(regs_base + RESIZABLE_BAR_CAP);
448 max_size = 1ULL << (5 + (reg + (1 << 4)));
449
450 if (size > max_size) {
451 size = max_size;
452 printf("Warning: PCIe BARs can't map all DRAM space\n");
453 }
454
455 /* Set the BAR base and size towards DDR */
456 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
457 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
458 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
459
460 reg = ((size >> 20) - 1) << 12;
461 writel(size, regs_base + RESIZABLE_BAR_CTL0);
462 }
463
464 /**
465 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
466 *
467 * @dev: A pointer to the device being operated on
468 *
469 * Probe for an active link on the PCIe bus and configure the controller
470 * to enable this port.
471 *
472 * Return: 0 on success, else -ENODEV
473 */
pcie_dw_mvebu_probe(struct udevice * dev)474 static int pcie_dw_mvebu_probe(struct udevice *dev)
475 {
476 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
477 struct udevice *ctlr = pci_get_controller(dev);
478 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
479 #ifdef CONFIG_DM_GPIO
480 struct gpio_desc reset_gpio;
481
482 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
483 GPIOD_IS_OUT);
484 /*
485 * Issue reset to add-in card trough the dedicated GPIO.
486 * Some boards are connecting the card reset pin to common system
487 * reset wire and others are using separate GPIO port.
488 * In the last case we have to release a reset of the addon card
489 * using this GPIO.
490 */
491 if (dm_gpio_is_valid(&reset_gpio)) {
492 dm_gpio_set_value(&reset_gpio, 1); /* assert */
493 mdelay(200);
494 dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
495 mdelay(200);
496 }
497 #else
498 debug("PCIE Reset on GPIO support is missing\n");
499 #endif /* CONFIG_DM_GPIO */
500
501 pcie->first_busno = dev->seq;
502
503 /* Don't register host if link is down */
504 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
505 printf("PCIE-%d: Link down\n", dev->seq);
506 } else {
507 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
508 pcie_dw_get_link_speed(pcie->ctrl_base),
509 pcie_dw_get_link_width(pcie->ctrl_base),
510 hose->first_busno);
511 }
512
513 /* Store the IO and MEM windows settings for future use by the ATU */
514 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
515 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
516 pcie->io.size = hose->regions[0].size; /* IO size */
517
518 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
519 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
520 pcie->mem.size = hose->regions[1].size; /* MEM size */
521
522 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
523 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
524 pcie->mem.bus_start, pcie->mem.size);
525
526 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
527 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
528 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
529
530 pcie_dw_set_host_bars(pcie->ctrl_base);
531
532 return 0;
533 }
534
535 /**
536 * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
537 *
538 * @dev: A pointer to the device being operated on
539 *
540 * Translate relevant data from the device tree pertaining to device @dev into
541 * state that the driver will later make use of. This state is stored in the
542 * device's private data structure.
543 *
544 * Return: 0 on success, else -EINVAL
545 */
pcie_dw_mvebu_ofdata_to_platdata(struct udevice * dev)546 static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
547 {
548 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
549
550 /* Get the controller base address */
551 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
552 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
553 return -EINVAL;
554
555 /* Get the config space base address and size */
556 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
557 &pcie->cfg_size);
558 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
559 return -EINVAL;
560
561 return 0;
562 }
563
564 static const struct dm_pci_ops pcie_dw_mvebu_ops = {
565 .read_config = pcie_dw_mvebu_read_config,
566 .write_config = pcie_dw_mvebu_write_config,
567 };
568
569 static const struct udevice_id pcie_dw_mvebu_ids[] = {
570 { .compatible = "marvell,armada8k-pcie" },
571 { }
572 };
573
574 U_BOOT_DRIVER(pcie_dw_mvebu) = {
575 .name = "pcie_dw_mvebu",
576 .id = UCLASS_PCI,
577 .of_match = pcie_dw_mvebu_ids,
578 .ops = &pcie_dw_mvebu_ops,
579 .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
580 .probe = pcie_dw_mvebu_probe,
581 .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),
582 };
583