Lines Matching full:pcie
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
134 * @pcie: Pointer to the PCI controller state
138 * @pci_addr: the pcie bus address for the translation entry
141 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, in pcie_dw_prog_outbound_atu() argument
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
150 pcie->ctrl_base + PCIE_ATU_LIMIT); in pcie_dw_prog_outbound_atu()
152 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); in pcie_dw_prog_outbound_atu()
154 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); in pcie_dw_prog_outbound_atu()
155 writel(type, pcie->ctrl_base + PCIE_ATU_CR1); in pcie_dw_prog_outbound_atu()
156 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); in pcie_dw_prog_outbound_atu()
160 * set_cfg_address() - Configure the PCIe controller config space access
162 * @pcie: Pointer to the PCI controller state
166 * Configures the PCIe controller to access the configuration space of
167 * a specific PCIe device and returns the address to use for this
173 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, in set_cfg_address() argument
185 if (PCI_BUS(d) == (pcie->first_busno + 1)) in set_cfg_address()
192 if (PCI_BUS(d) == pcie->first_busno) { in set_cfg_address()
194 va_address = (uintptr_t)pcie->ctrl_base; in set_cfg_address()
196 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno); in set_cfg_address()
197 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, in set_cfg_address()
198 atu_type, (u64)pcie->cfg_base, in set_cfg_address()
199 d << 8, pcie->cfg_size); in set_cfg_address()
200 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
212 * @first_busno: Bus number of the PCIe controller root complex
232 * @bdf: Identifies the PCIe device to access
247 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); in pcie_dw_mvebu_read_config() local
251 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", in pcie_dw_mvebu_read_config()
254 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { in pcie_dw_mvebu_read_config()
260 va_address = set_cfg_address(pcie, bdf, offset); in pcie_dw_mvebu_read_config()
267 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, in pcie_dw_mvebu_read_config()
268 PCIE_ATU_TYPE_IO, pcie->io.phys_start, in pcie_dw_mvebu_read_config()
269 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_read_config()
278 * @bdf: Identifies the PCIe device to access
293 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); in pcie_dw_mvebu_write_config() local
297 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", in pcie_dw_mvebu_write_config()
301 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { in pcie_dw_mvebu_write_config()
306 va_address = set_cfg_address(pcie, bdf, offset); in pcie_dw_mvebu_write_config()
312 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, in pcie_dw_mvebu_write_config()
313 PCIE_ATU_TYPE_IO, pcie->io.phys_start, in pcie_dw_mvebu_write_config()
314 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_write_config()
322 * @regs_base: A pointer to the PCIe controller registers
325 * Configure the link capabilities and speed in the PCIe root complex.
332 * configure the PCIe gen in pcie_dw_configure()
346 * @regs_base: A pointer to the PCIe controller registers
365 * @regs_base: A pointer to the PCIe controller registers
383 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
385 * @regs_base: A pointer to the PCIe controller registers
388 * Configure the PCIe controller root complex depending on the
405 /* Set the PCIe master AXI attributes */ in pcie_dw_mvebu_pcie_link_up()
434 * @regs_base: A pointer to the PCIe controller registers
436 * Configure the host BARs of the PCIe controller root port so that
452 printf("Warning: PCIe BARs can't map all DRAM space\n"); in pcie_dw_set_host_bars()
465 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
469 * Probe for an active link on the PCIe bus and configure the controller
476 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); in pcie_dw_mvebu_probe() local
498 debug("PCIE Reset on GPIO support is missing\n"); in pcie_dw_mvebu_probe()
501 pcie->first_busno = dev->seq; in pcie_dw_mvebu_probe()
504 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { in pcie_dw_mvebu_probe()
505 printf("PCIE-%d: Link down\n", dev->seq); in pcie_dw_mvebu_probe()
507 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, in pcie_dw_mvebu_probe()
508 pcie_dw_get_link_speed(pcie->ctrl_base), in pcie_dw_mvebu_probe()
509 pcie_dw_get_link_width(pcie->ctrl_base), in pcie_dw_mvebu_probe()
514 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ in pcie_dw_mvebu_probe()
515 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ in pcie_dw_mvebu_probe()
516 pcie->io.size = hose->regions[0].size; /* IO size */ in pcie_dw_mvebu_probe()
518 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ in pcie_dw_mvebu_probe()
519 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ in pcie_dw_mvebu_probe()
520 pcie->mem.size = hose->regions[1].size; /* MEM size */ in pcie_dw_mvebu_probe()
522 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, in pcie_dw_mvebu_probe()
523 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, in pcie_dw_mvebu_probe()
524 pcie->mem.bus_start, pcie->mem.size); in pcie_dw_mvebu_probe()
527 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, in pcie_dw_mvebu_probe()
530 pcie_dw_set_host_bars(pcie->ctrl_base); in pcie_dw_mvebu_probe()
548 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); in pcie_dw_mvebu_ofdata_to_platdata() local
551 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); in pcie_dw_mvebu_ofdata_to_platdata()
552 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE) in pcie_dw_mvebu_ofdata_to_platdata()
556 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, in pcie_dw_mvebu_ofdata_to_platdata()
557 &pcie->cfg_size); in pcie_dw_mvebu_ofdata_to_platdata()
558 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) in pcie_dw_mvebu_ofdata_to_platdata()
570 { .compatible = "marvell,armada8k-pcie" },