Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01 |
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baa29d5e |
| 18-Jul-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Merge remote-tracking branch 'origin/aspeed-dev-v2019.04' into aspeed-master-v2019.04
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Revision tags: v2019.07 |
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befc1c99 |
| 02-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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09fa5f07 |
| 21-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
add pcie driver
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Revision tags: v00.02.00, v2019.04 |
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bdac5e18 |
| 05-Feb-2019 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me - Move Armada XP / 38x LCD driver to DM_VIDEO from me - Add uDPU board (Armada-3720) from Vladimir
[trini
Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me - Move Armada XP / 38x LCD driver to DM_VIDEO from me - Add uDPU board (Armada-3720) from Vladimir
[trini: Fix warning in pci-uclass.c by removing ret from pci_uclass_child_post_bind as it no longer calls functions with a return code to catch.] Signed-off-by: Tom Rini <trini@konsulko.com>II
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94f453ea |
| 25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (dr
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release.
To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
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Revision tags: v2018.07 |
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7c45862f |
| 20-Apr-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
pci: intel: Add Intel FPGA PCIe controller driver
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested w
pci: intel: Add Intel FPGA PCIe controller driver
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested with the Intel e1000e NIC driver.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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f3b623fa |
| 30-Mar-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-marvell
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e51f2b14 |
| 26-Mar-2018 |
Wilson Ding <dingwei@marvell.com> |
arm64: a37xx: pci: add support for aardvark pcie driver
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports
arm64: a37xx: pci: add support for aardvark pcie driver
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width.
Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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Revision tags: v2018.03 |
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9c486e7c |
| 27-Jan-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh
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5f14f7d7 |
| 18-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
pci: rmobile: Add RCar Gen2 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as
pci: rmobile: Add RCar Gen2 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as access the on-SoC USB EHCI controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Revision tags: v2018.01, v2017.11 |
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3675cb04 |
| 19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Add driver for a 'pci-host-ecam-generic' host controller
QEMU emulates such a device with '-machine virt,highmem=off' on ARM. The 'highmem=off' part is required for things to work as the PCI co
PCI: Add driver for a 'pci-host-ecam-generic' host controller
QEMU emulates such a device with '-machine virt,highmem=off' on ARM. The 'highmem=off' part is required for things to work as the PCI code in U-Boot doesn't seem to support 64-bit BARs.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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44913a18 |
| 01-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Remove unnecessary 'default n' from Kconfig
'default n' is the default anyway so it doesn't need to be specified explicitly, and the rest of the file doesn't specify it either anywhere. Drop it
pci: Remove unnecessary 'default n' from Kconfig
'default n' is the default anyway so it doesn't need to be specified explicitly, and the rest of the file doesn't specify it either anywhere. Drop it.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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07d77838 |
| 01-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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6bf89de7 |
| 30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Select PCI and DM_PCI
PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Revi
x86: kconfig: Select PCI and DM_PCI
PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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0675f992 |
| 19-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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80afc63f |
| 13-Dec-2016 |
Minghuan Lian <Minghuan.Lian@nxp.com> |
pci: layerscape: add pci driver based on DM
There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro
pci: layerscape: add pci driver based on DM
There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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0ed06c7e |
| 04-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
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e090fdba |
| 19-Dec-2016 |
Marcel Ziswiler <marcel.ziswiler@toradex.com> |
pci: kconfig: fix spelling in description
Fix 'driver model' rather than 'driver mode' in description.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarre
pci: kconfig: fix spelling in description
Fix 'driver model' rather than 'driver mode' in description.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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f2465934 |
| 16-Dec-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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182ba1a7 |
| 27-Oct-2016 |
Shadi Ammouri <shadi@marvell.com> |
pci: mvebu: Add PCIe driver for Armada-8K
This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core.
The original
pci: mvebu: Add PCIe driver for Armada-8K
This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core.
The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support.
Tested on the Marvell DB-88F8040 Armada-8K eval board.
Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
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c4762157 |
| 17-Oct-2016 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Move CONFIG_PCI_PNP to Kconfig
Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsul
pci: Move CONFIG_PCI_PNP to Kconfig
Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
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af27382e |
| 26-Oct-2016 |
Tom Rini <trini@konsulko.com> |
drivers/pci/Kconfig: Add PCI
Add 'PCI' as a menu option and migrate all existing users.
Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
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423620b9 |
| 21-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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a29e45a9 |
| 08-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge
This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is
pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge
This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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bbc5b36b |
| 05-Aug-2016 |
Stephen Warren <swarren@nvidia.com> |
pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver
pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs.
On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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