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/openbmc/qemu/docs/
H A Dqcow2-cache.txt1 qcow2 L2/refcount cache configuration
3 Copyright (C) 2015, 2018-2020 Igalia, S.L.
7 later. See the COPYING file in the top-level directory.
10 ------------
12 performance significantly. However, setting the right cache sizes is
15 This document attempts to give an overview of the L2 and refcount
18 Please refer to the docs/interop/qcow2.rst file for an in-depth
23 --------
30 The 'qemu-img create' command supports specifying the size using the
33 qemu-img create -f qcow2 -o cluster_size=128K hd.qcow2 4G
[all …]
/openbmc/qemu/block/
H A Dqed-l2-cache.c2 * QEMU Enhanced Disk Format L2 Cache
10 * See the COPYING.LIB file in the top-level directory.
15 * L2 table cache usage is as follows:
17 * An open image has one L2 table cache that is used to avoid accessing the
18 * image file for recently referenced L2 tables.
22 * the L1 and L2 tables which store cluster offsets. It is here where the L2
23 * table cache serves up recently referenced L2 tables.
25 * If there is a cache miss, that L2 table is read from the image file and
26 * committed to the cache. Subsequent accesses to that L2 table will be served
27 * from the cache until the table is evicted from the cache.
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H A Dqed-cluster.c11 * See the COPYING.LIB file in the top-level directory.
22 * @table: L2 table
36 unsigned int end = MIN(index + n, s->table_nelems); in qed_count_contiguous_clusters()
37 uint64_t last = table->offsets[index]; in qed_count_contiguous_clusters()
45 if (!qed_offset_is_unalloc_cluster(table->offsets[i])) { in qed_count_contiguous_clusters()
50 if (!qed_offset_is_zero_cluster(table->offsets[i])) { in qed_count_contiguous_clusters()
55 if (table->offsets[i] != last + s->header.cluster_size) { in qed_count_contiguous_clusters()
58 last = table->offsets[i]; in qed_count_contiguous_clusters()
61 return i - index; in qed_count_contiguous_clusters()
68 * @request: L2 cache entry
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/openbmc/qemu/tests/qemu-iotests/
H A D1034 # Test case for qcow2 metadata cache size specification
44 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
49 $QEMU_IO -c 'write -P 42 0 64k' "$TEST_IMG" | _filter_qemu_io
56 $QEMU_IO -c "open -o cache-size=1.25M,l2-cache-size=1M,refcount-cache-size=0.25M $TEST_IMG" \
58 # l2-cache-size may not exceed cache-size
59 $QEMU_IO -c "open -o cache-size=1M,l2-cache-size=2M $TEST_IMG" 2>&1 \
61 # refcount-cache-size may not exceed cache-size
62 $QEMU_IO -c "open -o cache-size=1M,refcount-cache-size=2M $TEST_IMG" 2>&1 \
66 $QEMU_IO -c "open -o cache-size=0,l2-cache-size=0,refcount-cache-size=0 $TEST_IMG" \
69 # Invalid cache entry sizes
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H A D13744 # We are going to use lazy-refcounts
56 -c "reopen -o lazy-refcounts=on,pass-discard-request=on" \
57 -c "reopen -o lazy-refcounts=off,pass-discard-request=off" \
58 -c "reopen -o pass-discard-snapshot=on,pass-discard-other=on" \
59 -c "reopen -o pass-discard-snapshot=off,pass-discard-other=off" \
60 -c "reopen -o overlap-check=all" \
61 -c "reopen -o overlap-check=none" \
62 -c "reopen -o overlap-check=cached" \
63 -c "reopen -o overlap-check=constant" \
64 -c "reopen -o overlap-check.template=all" \
[all …]
H A D103.out8 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
9 qemu-io: can't open device TEST_DIR/t.IMGFMT: l2-cache-size may not exceed cache-size
10 qemu-io: can't open device TEST_DIR/t.IMGFMT: refcount-cache-size may not exceed cache-size
11 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
12 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
13 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
14 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
33 === Testing minimal L2 cache and COW ===
H A D026.out.nocache11 Event: l1_update; errno: 5; imm: off; once: on; write -b
17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
41 qemu-io: Failed to flush the L2 table cache: No space left on device
42 qemu-io: Failed to flush the refcount block cache: No space left on device
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
[all …]
H A D026.out11 Event: l1_update; errno: 5; imm: off; once: on; write -b
17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
41 qemu-io: Failed to flush the L2 table cache: No space left on device
42 qemu-io: Failed to flush the refcount block cache: No space left on device
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
[all …]
H A D137.out18 qemu-io: Parameter 'lazy-refcounts' expects 'on' or 'off'
19 qemu-io: cache-size, l2-cache-size and refcount-cache-size may not be set at the same time
20 qemu-io: l2-cache-size may not exceed cache-size
21 qemu-io: refcount-cache-size may not exceed cache-size
22 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
23 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
24 qemu-io: Refcount cache size too big
25 qemu-io: Conflicting values for qcow2 options 'overlap-check' ('constant') and 'overlap-check.templ…
26 qemu-io: Unsupported value 'blubb' for qcow2 option 'overlap-check'. Allowed are any of the followi…
27 qemu-io: Unsupported value 'blubb' for qcow2 option 'overlap-check'. Allowed are any of the followi…
[all …]
/openbmc/u-boot/arch/mips/lib/
H A Dcache_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Cache-handling routined for MIPS CPUs
8 #include <asm-offsets.h>
39 10: cache \op, 0(\curr)
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
59 srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
67 srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
83 * mips_cache_reset - low level initialisation of the primary caches
89 * To initialise the instruction cache it is essential that a source of data
94 * may clobber typically callee-saved registers.
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H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
40 gd->arch.l2_line_size = mips_cm_l2_line_size(); in probe_l2()
42 /* We don't know how to retrieve L2 config on this system */ in probe_l2()
46 gd->arch.l2_line_size = sl ? (2 << sl) : 0; in probe_l2()
61 gd->arch.l1i_line_size = il ? (2 << il) : 0; in mips_cache_probe()
62 gd->arch.l1d_line_size = dl ? (2 << dl) : 0; in mips_cache_probe()
70 return gd->arch.l1i_line_size; in icache_line_size()
79 return gd->arch.l1d_line_size; in dcache_line_size()
88 return gd->arch.l2_line_size; in scache_line_size()
95 const void *addr = (const void *)(start & ~(lsize - 1)); \
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/openbmc/u-boot/arch/arm/dts/
H A Dbcm6858.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dbcm63158.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 next-level-cache = <&l2>;
[all …]
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S7 #include <asm/cache.h>
23 # error "Invalid cache line size!"
27 * Most of this code is taken from 74xx_7xx/cache.S
32 * Invalidate L1 instruction cache.
35 /* use invalidate-all bit in HID0 */
43 * Invalidate L1 data cache.
53 * Flush data cache.
68 * Write any modified data cache blocks out to memory
69 * and invalidate the corresponding instruction cache blocks.
70 * This is a no-op on the 601.
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/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
10 L2 cache
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
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/openbmc/qemu/qapi/
H A Dmachine-common.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
57 # topology settings (e.g., cache topology), and this special
58 # level means following the architecture-specific settings.
70 # combination of cache level and cache type.
72 # @l1d: L1 data cache.
74 # @l1i: L1 instruction cache.
76 # @l2: L2 (unified) cache.
78 # @l3: L3 (unified) cache
83 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] }
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/openbmc/u-boot/arch/arm/mach-imx/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/mach-imx/sys_proto.h>
51 /* Set ACTLR.SMP bit for Cortex-A7 */ in enable_caches()
54 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
69 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are in enable_caches()
70 * disabled by u-boot in enable_caches()
89 * Must disable the L2 before changing the latency parameters in v7_outer_cache_enable()
92 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
96 * is cleared, PL310 treats Normal Shared Non-cacheable in v7_outer_cache_enable()
97 * accesses as Cacheable no-allocate. in v7_outer_cache_enable()
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h2 * include/asm-ppc/cache.h
9 /* bytes per L1 cache line */
23 * Use the L1 data cache line size value for the minimum DMA buffer alignment
35 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
66 /* prep registers for L2 */
67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
76 /* Cache control on the MPC8xx is provided through some additional
79 #define IC_CST 560 /* Instruction cache control/status */
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H A Dimmap_85xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
47 /* Local-Access Registers & ECM Registers */
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
278 /* L2 Cache Registers */
280 u32 l2ctl; /* L2 configuration 0 */
282 u32 l2cewar0; /* L2 cache external write addr 0 */
284 u32 l2cewcr0; /* L2 cache external write control 0 */
286 u32 l2cewar1; /* L2 cache external write addr 1 */
288 u32 l2cewcr1; /* L2 cache external write control 1 */
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dcache.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
16 * Invalidate L2 Cache using co-proc instruction
25 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" in invalidate_l2_cache()
45 * The value of the largest data cache relevant to DMA operations shall be set
47 * value than found in the L1 cache but this is OK to use in terms of
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra cache routines */
10 #include <asm/arch-tegra/ap.h>
24 /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ in config_cache()
29 * Systems with an architectural L2 cache must not use the PL310. in config_cache()
/openbmc/u-boot/doc/
H A DREADME.mpc74xx1 This file contains status information for the port of U-Boot to the
10 There is a framework in place to enable the L2 cache, and to program
12 sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
17 Most of the code was based on other cpus supported by U-Boot.

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