L2\-cache (full) in projects: openbmc - OpenGrok search results

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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A D	freescale-l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 8 - compatible : Should include one of the following: 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	cache.json	5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all… 11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har… 17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all… 23 "BriefDescription": "Demand data cache fills from local L2 cache.", 29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.", 35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the… 41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.", 47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d… 53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa… 59 "BriefDescription": "Demand data cache fills from extension memory.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab… 15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache." 20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another… 25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." 30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs." 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach… 64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… [all …]
H A D	recommended.json	4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 12 "BriefDescription": "All L1 Data Cache Accesses", 17 "BriefDescription": "All L2 Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 35 "BriefDescription": "L2 Cache Accesses from L2 HWPF", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 HWPF", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	recommended.json	4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 12 "BriefDescription": "All L1 Data Cache Accesses", 17 "BriefDescription": "All L2 Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 35 "BriefDescription": "L2 Cache Accesses from L2 HWPF", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	recommended.json	4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 12 "BriefDescription": "All L1 Data Cache Accesses", 17 "BriefDescription": "All L2 Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 35 "BriefDescription": "L2 Cache Accesses from L2 HWPF", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 HWPF", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	cache.json	10 "BriefDescription": "L1 Cache evictions for dirty data", 13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem… 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i… 33 "BriefDescription": "L2 cache request misses", 36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 41 "BriefDescription": "L2 cache requests", 44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", 54 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	10 "BriefDescription": "L1 Cache evictions for dirty data", 13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem… 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i… 33 "BriefDescription": "L2 cache request misses", 36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 41 "BriefDescription": "L2 cache requests", 44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", 54 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… [all …]
/openbmc/qemu/docs/
H A D	qcow2-cache.txt	1 qcow2 L2/refcount cache configuration 3 Copyright (C) 2015, 2018-2020 Igalia, S.L. 7 later. See the COPYING file in the top-level directory. 10 ------------ 12 performance significantly. However, setting the right cache sizes is 15 This document attempts to give an overview of the L2 and refcount 18 Please refer to the docs/interop/qcow2.txt file for an in-depth 23 -------- 30 The 'qemu-img create' command supports specifying the size using the 33 qemu-img create -f qcow2 -o cluster_size=128K hd.qcow2 4G [all …]
/openbmc/qemu/block/
H A D	qed-l2-cache.c	2 * QEMU Enhanced Disk Format L2 Cache 10 * See the COPYING.LIB file in the top-level directory. 15 * L2 table cache usage is as follows: 17 * An open image has one L2 table cache that is used to avoid accessing the 18 * image file for recently referenced L2 tables. 22 * the L1 and L2 tables which store cluster offsets. It is here where the L2 23 * table cache serves up recently referenced L2 tables. 25 * If there is a cache miss, that L2 table is read from the image file and 26 * committed to the cache. Subsequent accesses to that L2 table will be served 27 * from the cache until the table is evicted from the cache. [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev… 105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev… 108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that… 111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that… 114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami… 117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami… 120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr… 123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry… 126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming … 129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming … [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 45 "BriefDescription": "Not rejected writebacks that hit L2 cache", 48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 53 "BriefDescription": "L2 cache lines filling L2", 56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does… 61 "BriefDescription": "L2 cache lines in E state filling L2", 64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th… 69 "BriefDescription": "L2 cache lines in I state filling L2", 72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	3 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 54 "BriefDescription": "L2 cache lines filling L2", 57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 62 …"BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cac… 65 …iption": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fi… 70 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	cache.json	6 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 69 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from… 77 "BriefDescription": "L2 cache lines filling L2", 80 "PublicDescription": "L2 cache lines filling L2.", 85 "BriefDescription": "L2 cache lines in E state filling L2", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	cache.json	6 …en new data lines are brought into the L1 Data cache, which cause other lines to be evicted from t… 51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 59 "BriefDescription": "L2 cache lines filling L2", 62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2… 67 "BriefDescription": "L2 cache lines in E state filling L2", 70 "PublicDescription": "L2 cache lines in E state filling L2.", 75 "BriefDescription": "L2 cache lines in I state filling L2", 78 "PublicDescription": "L2 cache lines in I state filling L2.", 83 "BriefDescription": "L2 cache lines in S state filling L2", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	cache.json	6 …en new data lines are brought into the L1 Data cache, which cause other lines to be evicted from t… 51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 59 "BriefDescription": "L2 cache lines filling L2", 62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2… 67 "BriefDescription": "L2 cache lines in E state filling L2", 70 "PublicDescription": "L2 cache lines in E state filling L2.", 75 "BriefDescription": "L2 cache lines in I state filling L2", 78 "PublicDescription": "L2 cache lines in I state filling L2.", 83 "BriefDescription": "L2 cache lines in S state filling L2", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	cache.json	3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a… 6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L… 21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 … 25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request… 32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a… 6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L… 21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 … 25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request… 32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	10 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 69 "BriefDescription": "L2 cache lines filling L2", 72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 84 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 87 …re silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in S… 92 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 45 "BriefDescription": "Not rejected writebacks that hit L2 cache", 48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 53 "BriefDescription": "L2 cache lines filling L2", 56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does… 61 "BriefDescription": "L2 cache lines in E state filling L2", 64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th… 69 "BriefDescription": "L2 cache lines in I state filling L2", 72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	cache.json	6 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 69 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from… 77 "BriefDescription": "L2 cache lines filling L2", 80 "PublicDescription": "L2 cache lines filling L2.", 85 "BriefDescription": "L2 cache lines in E state filling L2", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … [all …]
/openbmc/qemu/tests/qemu-iotests/
H A D	103	4 # Test case for qcow2 metadata cache size specification 44 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file 49 $QEMU_IO -c 'write -P 42 0 64k' "$TEST_IMG" \| _filter_qemu_io 56 $QEMU_IO -c "open -o cache-size=1.25M,l2-cache-size=1M,refcount-cache-size=0.25M $TEST_IMG" \ 58 # l2-cache-size may not exceed cache-size 59 $QEMU_IO -c "open -o cache-size=1M,l2-cache-size=2M $TEST_IMG" 2>&1 \ 61 # refcount-cache-size may not exceed cache-size 62 $QEMU_IO -c "open -o cache-size=1M,refcount-cache-size=2M $TEST_IMG" 2>&1 \ 66 $QEMU_IO -c "open -o cache-size=0,l2-cache-size=0,refcount-cache-size=0 $TEST_IMG" \ 69 # Invalid cache entry sizes [all …]

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