x86/amdzen3/cache.json

5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
82 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-…
88 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
94     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
100     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
106 …"BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divide…
112 …"BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining …
118 …"BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining …
124 …"BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write …
130 …"BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Wri…
136 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data c…
142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
148 …escription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache r…
154 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache …
160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
166 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction…
172 …scription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction c…
178 …iefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruct…
184 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instru…
190 …"Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request…
196 … "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache reques…
202 …ription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in …
208     "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.",
214 …"BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipelin…
220 …"BriefDescription": "L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipel…
226 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
236 …Description": "Instruction Cache Refills from L2. The number of 64 byte instruction cache line was…
241 …on": "Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfille…
246 …iefDescription": "L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1…
251     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs.",
257 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
263 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
269 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
275 …s into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-IT…
281 … instruction stream was being modified by another processor in an MP system - typically a highly u…
298 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
304 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
310 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
316 …"BriefDescription": "All Instruction Cache Accesses. Counts various IC tag related hit and miss ev…
322 …  "BriefDescription": "Instruction Cache Miss. Counts various IC tag related hit and miss events.",
328     "BriefDescription": "Instruction Cache Hit. Counts various IC tag related hit and miss events.",
346     "BriefDescription": "All Op Cache accesses. Counts Op Cache micro-tag hit/miss events",
352     "BriefDescription": "Op Cache Miss. Counts Op Cache micro-tag hit/miss events",
358     "BriefDescription": "Op Cache Hit. Counts Op Cache micro-tag hit/miss events",
364     "BriefDescription": "Caching: L3 cache accesses",
371     "BriefDescription": "All L3 Request Types. All L3 cache Requests",
385     "BriefDescription": "L3 cache misses",
392 …"BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignor…